FreeBSD/src ce3b53fsbin/nvmecontrol nvmecontrol.8

nvmecontrol: Flesh out nvmecontrol format information

The format command takes a number of different parameters. Include a
brief summary of what the values mean, though since the driver's support
for metadata is at best weak, 0's are almost always used for values
other than -f format. Add an example that ties it all together.

Sponsored by:           Netflix
Reviewed by:            pauamma at gundo.com, chuck
Differential Revision:  https://reviews.freebsd.org/D44958
DeltaFile
+70-11sbin/nvmecontrol/nvmecontrol.8
+70-111 files

LLVM/project 5f67ce5llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVInstrInfo.h, llvm/test/CodeGen/RISCV/rvv vector-reassociations.ll

[RISCV][MachineCombiner] Add reassociation optimizations for RVV instructions (#88307)

This patch covers a really basic reassociation optimizations for VADD_VV and VMUL_VV.
DeltaFile
+266-0llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+13-14llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
+14-0llvm/lib/Target/RISCV/RISCVInstrInfo.h
+293-143 files

LLVM/project b832e36

Rebase

Created using spr 1.3.4
DeltaFile
+0-00 files

LLVM/project 973748b

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+0-00 files

LLVM/project 733b271llvm/docs ReleaseNotes.rst, llvm/lib/Target/RISCV RISCVFeatures.td

[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to the recommendation
in

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc

This tag changes the default for the feature flag, and moves to more
consistent naming with respect to existing features.
DeltaFile
+8-8llvm/test/CodeGen/RISCV/atomic-load-store.ll
+6-6llvm/test/CodeGen/RISCV/forced-atomics.ll
+4-4llvm/lib/Target/RISCV/RISCVFeatures.td
+3-3llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+5-0llvm/docs/ReleaseNotes.rst
+2-2llvm/test/CodeGen/RISCV/attributes.ll
+28-231 files not shown
+29-247 files

LLVM/project b1b24abclang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

Rebase

Created using spr 1.3.4
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,738 files not shown
+595,230-317,7029,744 files

LLVM/project 0722154clang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,738 files not shown
+595,230-317,7029,744 files

FreeNAS/freenas 264f86fsrc/middlewared/middlewared/etc_files scst.conf.mako, src/middlewared/middlewared/plugins/iscsi_ targets.py

Add various iSCSI target parameters as options
DeltaFile
+43-0src/middlewared/middlewared/plugins/iscsi_/targets.py
+6-0src/middlewared/middlewared/etc_files/scst.conf.mako
+49-02 files

LLVM/project 9221f3alld/ELF/Arch RISCV.cpp, lld/test/ELF riscv-attributes.s

[RISCV] Support RISCV Atomics ABI attributes (#84597)

This patch adds support for the `atomic_abi` attribute, specifid in

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version.

The atomics_abi tag merging is conducted as follows:

- UNKNOWN is safe to merge with all other values.
- A6C is compatible with A6S, and results in the A6C ABI.
- A6C is incompatible with A7, and results in an error.
- A6S and A7 are compatible, and merging results in the A7 ABI.

Note: the A7 is not yet supported in either LLVM or in any current
hardware,
and is therefore ommited from attribute generation in
RISCVTargetStreamer.
DeltaFile
+202-0lld/test/ELF/riscv-attributes.s
+63-0lld/ELF/Arch/RISCV.cpp
+12-1llvm/lib/Support/RISCVAttributeParser.cpp
+13-0llvm/include/llvm/Support/RISCVAttributes.h
+9-1llvm/test/CodeGen/RISCV/attributes.ll
+7-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+306-24 files not shown
+314-210 files

LLVM/project 1302f97llvm/include/llvm/IR ProfDataUtils.h, llvm/lib/IR ProfDataUtils.cpp Instruction.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4
DeltaFile
+57-22llvm/lib/IR/ProfDataUtils.cpp
+15-15llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+26-4llvm/include/llvm/IR/ProfDataUtils.h
+12-10llvm/lib/Transforms/Utils/MisExpect.cpp
+13-4llvm/lib/IR/Instruction.cpp
+9-7llvm/lib/Transforms/Scalar/LowerExpectIntrinsic.cpp
+132-6223 files not shown
+209-11529 files

LLVM/project 29a95aellvm/include/llvm/IR ProfDataUtils.h, llvm/lib/IR ProfDataUtils.cpp Instruction.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.4

[skip ci]
DeltaFile
+55-22llvm/lib/IR/ProfDataUtils.cpp
+15-15llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+24-4llvm/include/llvm/IR/ProfDataUtils.h
+12-10llvm/lib/Transforms/Utils/MisExpect.cpp
+13-4llvm/lib/IR/Instruction.cpp
+9-7llvm/lib/Transforms/Scalar/LowerExpectIntrinsic.cpp
+128-6223 files not shown
+209-11529 files

LLVM/project 5fa167eclang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

Factor out misexpect changes

Created using spr 1.3.4
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,066 files not shown
+535,440-285,5899,072 files

LLVM/project f758bb6llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV unsigned-icmp-signed-op.ll

[SLP]Fix PR89988: do extra analysis of the icmp args to correctly handle signed/unsigned comparison.

If operands of icmp has different signedness, need to consider extending
unsigned operands to correctly handle comparison with the signed
operands.
DeltaFile
+8-3llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3-1llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
+11-42 files

LLVM/project e6c73c1clang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,065 files not shown
+535,439-285,5889,071 files

LLVM/project e5bd278clang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

Address comments

Created using spr 1.3.4
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,065 files not shown
+535,439-285,5889,071 files

LLVM/project 7b541e1clang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,064 files not shown
+535,419-285,5579,070 files

LLVM/project 4bdaf60llvm/include/llvm/IR ProfDataUtils.h, llvm/lib/IR ProfDataUtils.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.4

[skip ci]
DeltaFile
+27-15llvm/lib/IR/ProfDataUtils.cpp
+8-3llvm/include/llvm/IR/ProfDataUtils.h
+2-5llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+1-1llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
+38-244 files

LLVM/project 2e57140llvm/include/llvm/IR ProfDataUtils.h, llvm/lib/IR ProfDataUtils.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4
DeltaFile
+27-15llvm/lib/IR/ProfDataUtils.cpp
+8-3llvm/include/llvm/IR/ProfDataUtils.h
+2-5llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+2-1llvm/lib/Transforms/Utils/MisExpect.cpp
+1-1llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
+40-255 files

LLVM/project bef6687llvm/test/Transforms/SLPVectorizer/RISCV unsigned-icmp-signed-op.ll

[SLP][NFC]Add a test with the incorrect comparison after minbiwidth analysis.
DeltaFile
+41-0llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
+41-01 files

LLVM/project 90a2082libcxx/include/__utility no_destroy.h

undo __libcpp_is_constant_evaluated to fix
‘constexpr’ constructor does not have empty body
DeltaFile
+1-7libcxx/include/__utility/no_destroy.h
+1-71 files

LLVM/project 1bd331cclang/test/OpenMP nesting_of_regions.cpp, clang/test/OpenMP/Inputs nesting_of_regions.cpp

Rebase

Created using spr 1.3.4
DeltaFile
+0-19,580clang/test/OpenMP/nesting_of_regions.cpp
+19,567-0clang/test/OpenMP/Inputs/nesting_of_regions.cpp
+5,663-7,499llvm/test/CodeGen/WebAssembly/simd-arith.ll
+272-8,704llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+3,428-3,704llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+3,229-2,410llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+32,159-41,8979,064 files not shown
+535,419-285,5579,070 files

LLVM/project e0eb0f2libcxx/include/__utility no_destroy.h

fix build
DeltaFile
+2-1libcxx/include/__utility/no_destroy.h
+2-11 files

LLVM/project db440d8libcxx/include/__utility no_destroy.h

construct with 0
DeltaFile
+1-1libcxx/include/__utility/no_destroy.h
+1-11 files

LLVM/project 7cacaadlibcxx/test/libcxx/utilities no_destroy.pass.cpp

reorder test
DeltaFile
+5-6libcxx/test/libcxx/utilities/no_destroy.pass.cpp
+5-61 files

LLVM/project 4ce1313libcxx/include/__utility no_destroy.h

init only for __libcpp_is_constant_evaluated
DeltaFile
+6-1libcxx/include/__utility/no_destroy.h
+6-11 files

LLVM/project 475b9a9libcxx/test/libcxx/utilities no_destroy.pass.cpp

Inline test
DeltaFile
+2-3libcxx/test/libcxx/utilities/no_destroy.pass.cpp
+2-31 files

LLVM/project a27de45libcxx/include/__utility no_destroy.h

Remove "unsigned"
DeltaFile
+1-1libcxx/include/__utility/no_destroy.h
+1-11 files

LLVM/project 538570clibcxx/include/__utility no_destroy.h, libcxx/test/libcxx/utilities no_destroy.pass.cpp

Move field initialized and add constinit test
DeltaFile
+5-0libcxx/test/libcxx/utilities/no_destroy.pass.cpp
+2-2libcxx/include/__utility/no_destroy.h
+7-22 files

LLVM/project 681a2d8libcxx/include/__utility no_destroy.h, libcxx/test/libcxx/utilities no_destroy.pass.cpp

[libcxx] Remove empty ~__no_destroy

Primary motivation is that after #84651 msan will
complain if fields accessed after ~__no_destroy.

Previously msan assumed that __obj_ will have own
destructor, were we will poison the field, but it never
happened before.

After #84651 msan will complain on any field access
after `~__no_destroy`.

As is Msan does validate fields destruction order for
classes with trivial destructor.

Additionally empty destructor will register __cxa_atexit with -O0.
https://gcc.godbolt.org/z/hce587b65

We can not remove the destructor with union where

    [9 lines not shown]
DeltaFile
+11-20libcxx/include/__utility/no_destroy.h
+28-0libcxx/test/libcxx/utilities/no_destroy.pass.cpp
+39-202 files

LLVM/project fd59319llvm/test/CodeGen/RISCV/rvv vector-reassociations.ll

[RISCV][MachineCombiner] Pre-commit test for RVV reassociations

This is the pre-commit test for PR #88307.
DeltaFile
+254-0llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
+254-01 files