+805 | -0 | test/CodeGen/X86/regalloc-copy-hints.mir |
+418 | -0 | test/CodeGen/Mips/llvm-ir/fptosi.ll |
+230 | -0 | test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir |
+167 | -0 | test/CodeGen/AMDGPU/r600.add.ll |
+164 | -0 | test/CodeGen/X86/PR40322.ll |
+152 | -0 | test/CodeGen/AMDGPU/r600.sub.ll |
+42 | -48 | test/CodeGen/AMDGPU/sub.ll |
+22 | -61 | test/CodeGen/AMDGPU/add.ll |
+41 | -32 | lib/Target/AMDGPU/SIFoldOperands.cpp |
+56 | -16 | test/CodeGen/X86/fast-isel-nontemporal.ll |
+64 | -8 | test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir |
+68 | -0 | test/CodeGen/Mips/pseudo-jump-fill.ll |
+63 | -0 | test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll |
+0 | -53 | lib/Target/AArch64/AArch64SchedPredicates.td |
+43 | -0 | test/tools/llvm-objdump/PowerPC/branch-offset.s |
+37 | -0 | test/tools/llvm-objdump/elf-symbol-visibility.test |
+18 | -18 | lib/Target/AArch64/AArch64SchedExynosM4.td |
+24 | -11 | lib/Target/Mips/MipsFastISel.cpp |
+35 | -0 | test/CodeGen/ARM/tail-call-scheduling.ll |
+34 | -0 | test/MC/PowerPC/ppc64-localentry-symbols.s |
+30 | -0 | test/CodeGen/AVR/hardware-mul.ll |
+4 | -26 | lib/Target/ARM/ARMISelLowering.cpp |
+24 | -6 | lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp |
+24 | -6 | tools/llvm-objdump/llvm-objdump.cpp |
+0 | -28 | test/CodeGen/AVR/mul.ll |
+28 | -0 | test/CodeGen/AVR/software-mul.ll |
+17 | -11 | lib/Target/AVR/AVRISelLowering.cpp |
+26 | -0 | test/CodeGen/WebAssembly/varargs.ll |
+23 | -0 | test/CodeGen/Mips/Fast-ISel/pr40325.ll |
+23 | -0 | test/CodeGen/SPARC/fp128.ll |
+20 | -0 | docs/ReleaseNotes.rst |
+3 | -9 | lib/Target/AMDGPU/VOP2Instructions.td |
+10 | -2 | lib/Target/AVR/AVRSubtarget.cpp |
+0 | -11 | lib/Target/AArch64/AArch64SchedPredExynos.td |
+9 | -1 | cmake/modules/LLVMProcessSources.cmake |
+10 | -0 | test/MC/WebAssembly/null-output.s |
+6 | -3 | lib/Target/WebAssembly/WebAssemblyISelLowering.cpp |
+7 | -1 | lib/Target/AVR/AVRISelLowering.h |
+8 | -0 | lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp |
+8 | -0 | test/CodeGen/Mips/abiflags32.ll |
+7 | -1 | lib/MC/WasmObjectWriter.cpp |
+5 | -2 | lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp |
+5 | -2 | lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp |
+3 | -3 | utils/git-svn/git-llvm |
+5 | -1 | lib/Target/X86/X86TargetMachine.cpp |
+4 | -2 | test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll |
+6 | -0 | lib/CodeGen/TargetRegisterInfo.cpp |
+5 | -0 | lib/Target/Mips/MicroMipsInstrFPU.td |
+4 | -1 | lib/Target/AVR/AVRSubtarget.h |
+2 | -2 | lib/Target/Sparc/SparcRegisterInfo.cpp |
+2 | -2 | test/tools/llvm-objdump/AMDGPU/source-lines.ll |
+2 | -2 | lib/Target/PowerPC/PPCISelDAGToDAG.cpp |
+4 | -0 | test/CodeGen/PowerPC/ppc32-pic-large.ll |
+3 | -1 | lib/Target/Mips/MicroMips32r6InstrInfo.td |
+2 | -2 | test/tools/llvm-objdump/eh_frame-coff.test |
+3 | -1 | lib/Target/Mips/MipsDSPInstrInfo.td |
+2 | -2 | lib/DebugInfo/DWARF/DWARFDebugFrame.cpp |
+3 | -0 | utils/release/merge-request.sh |
+2 | -1 | lib/Target/Mips/MipsAsmPrinter.cpp |
+3 | -0 | lib/Target/Mips/MipsSEInstrInfo.cpp |
+3 | -0 | lib/Target/PowerPC/PPCSubtarget.cpp |
+2 | -1 | test/CodeGen/AMDGPU/fence-barrier.ll |
+2 | -1 | test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll |
+2 | -1 | test/CodeGen/Mips/Fast-ISel/icmpbr1.ll |
+3 | -0 | test/tools/llvm-dlltool/coff-weak-exports.def |
+1 | -1 | test/CodeGen/AVR/umul-with-overflow.ll |
+1 | -1 | test/CodeGen/AMDGPU/salu-to-valu.ll |
+1 | -1 | lib/Target/X86/X86FastISel.cpp |
+1 | -1 | CMakeLists.txt |
+2 | -0 | lib/Target/PowerPC/PPCInstrInfo.td |
+1 | -1 | lib/MC/MCWin64EH.cpp |
+1 | -1 | utils/lit/lit/__init__.py |
+1 | -1 | test/CodeGen/AVR/smul-with-overflow.ll |
+2 | -0 | test/tools/llvm-objdump/PowerPC/lit.local.cfg |
+1 | -1 | lib/Object/COFFImportFile.cpp |
+1 | -0 | lib/Target/Mips/MipsDelaySlotFiller.cpp |
+1 | -0 | cmake/modules/AddLLVM.cmake |
+1 | -0 | lib/MC/ELFObjectWriter.cpp |