LLVM/project 62447ef — clang/lib/Sema SemaChecking.cpp, clang/test/CodeGen complex_Float16.c

by Joseph Huber via GitHub on ⎇
[Clang] Permit half precision in `__builtin_complex` (#156479)

Summary:
This was forbidden previously, which made us divergent with the GCC
implementation. Permit this by simply removing this Sema check.

Fixes: https://github.com/llvm/llvm-project/issues/156463
DeltaFile
+22-0clang/test/CodeGen/complex_Float16.c
+0-10clang/lib/Sema/SemaChecking.cpp
+0-7clang/test/Sema/fp16-sema.c
+0-7clang/test/Sema/riscv-fp16.c
+2-1clang/test/Sema/Float16.c
+24-255 files

LLVM/project 96e4caa — llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU si-fold-aligned-vgprs.mir si-fold-aligned-agprs.mir

by Matt Arsenault via GitHub on ⎇
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)

Perform a register class constraint check when performing the fold
DeltaFile
+55-9llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
+35-24llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+6-9llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
+96-423 files

LLVM/project ad4594e — llvm/include/llvm/Transforms/Utils SimplifyLibCalls.h, llvm/lib/Transforms/Utils SimplifyLibCalls.cpp

by Teresa Johnson via GitHub on ⎇
[MemProf] Allow hint update on existing calls to nobuiltin hot/cold new (#156476)

Explicit calls to ::operator new are marked nobuiltin and cannot be
elided or updated as they may call user defined versions. However,
existing calls to the hot/cold versions of new only need their hint
parameter value updated, which does not mutate the call.
DeltaFile
+86-0llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
+36-2llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+1-0llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
+123-23 files

LLVM/project 96c2776 — clang/test/Modules implicit-opt-level.c, llvm/clang/test/Modules implicit-opt-level.c

by Jan Svoboda on ⎇
[llvm][clang] Move a stray test into the Clang subdirectory
DeltaFile
+15-0clang/test/Modules/implicit-opt-level.c
+0-15llvm/clang/test/Modules/implicit-opt-level.c
+15-152 files

LLVM/project 8c958c2 — llvm/test/MC/AMDGPU vop3-literal.s

by Jay Foad via GitHub on ⎇
[AMDGPU] Autogenerate VOP3 literal checks (#156038)
DeltaFile
+185-182llvm/test/MC/AMDGPU/vop3-literal.s
+185-1821 files

LLVM/project 098f887 — llvm/lib/Target/AArch64 SMEInstrFormats.td AArch64InstrFormats.td, llvm/lib/Target/AArch64/Disassembler AArch64Disassembler.cpp

by Sergei Barannikov on ⎇
[AArch64] Remove post-decoding instruction mutations

These instructions can now be fully decoded automatically.
DeltaFile
+55-1llvm/lib/Target/AArch64/SMEInstrFormats.td
+22-27llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+17-13llvm/lib/Target/AArch64/AArch64InstrFormats.td
+6-2llvm/lib/Target/AArch64/SVEInstrFormats.td
+0-6llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
+1-2llvm/lib/Target/AArch64/CMakeLists.txt
+101-516 files

LLVM/project f7326ba — llvm/lib/Target/AArch64 CMakeLists.txt AArch64SystemOperands.td, llvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp

by Sergei Barannikov on ⎇
[AArch64] Correctly disassemble TSB instruction

TSB instruction has one operand, but the generated disassembler didn't
decode this operand. AArch64InstPrinter had a workaround for this.

This instruction can now be disassembled correctly.
DeltaFile
+0-7llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+1-2llvm/lib/Target/AArch64/CMakeLists.txt
+1-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+2-103 files

LLVM/project 7112890 — llvm/lib/Target/AArch64 SMEInstrFormats.td, llvm/lib/Target/AArch64/Disassembler AArch64Disassembler.cpp

by Sergei Barannikov on ⎇
[AArch64] Provide a custom decoder for LDR_ZA/STR_ZA

These are the only instructions that encode two operands in the same
field. Instead of fixing them after they have been incorrectly decoded,
provide a custom decoder.
DeltaFile
+19-10llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+4-0llvm/lib/Target/AArch64/SMEInstrFormats.td
+23-102 files

LLVM/project 6ff221b — llvm/lib/Target/AVR AVRInstrInfo.td CMakeLists.txt, llvm/lib/Target/AVR/Disassembler AVRDisassembler.cpp

by Sergei Barannikov on ⎇
[AVR] Remove workarounds for instructions using Z register

The generated disassembler can now correctly decode these instructions.
DeltaFile
+0-17llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+5-0llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+3-1llvm/lib/Target/AVR/AVRInstrInfo.td
+1-2llvm/lib/Target/AVR/CMakeLists.txt
+1-0llvm/lib/Target/AVR/AVRInstrFormats.td
+10-205 files

LLVM/project fd7e685 — llvm/lib/Target/RISCV RISCVInstrInfoC.td RISCVInstrInfoXwch.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

by Sergei Barannikov on ⎇
[RISCV] Remove post-decoding instruction adjustments
DeltaFile
+6-17llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+6-2llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+4-0llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td
+1-2llvm/lib/Target/RISCV/CMakeLists.txt
+0-1llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+17-225 files

LLVM/project 1230672 — llvm/lib/Target/AArch64 CMakeLists.txt, llvm/lib/Target/AMDGPU CMakeLists.txt

by Sergei Barannikov on ⎇
[TableGen][Decoder] Decode operands with zero width or all bits known
DeltaFile
+76-23llvm/utils/TableGen/DecoderEmitter.cpp
+10-0llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
+4-4llvm/lib/Target/Sparc/SparcInstrInfo.td
+3-1llvm/lib/Target/AArch64/CMakeLists.txt
+3-1llvm/lib/Target/AMDGPU/CMakeLists.txt
+2-1llvm/lib/Target/CSKY/CMakeLists.txt
+98-309 files not shown
+112-3915 files

LLVM/project b48ce40 — llvm/lib/Target/Hexagon HexagonDepInstrFormats.td HexagonOperands.td, llvm/lib/Target/Hexagon/Disassembler HexagonDisassembler.cpp

by Sergei Barannikov on ⎇
[Hexagon] Remove post-decoding instruction adjustments

These instructions can now be fully decoded automatically.
DeltaFile
+27-102llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td
+10-52llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+8-2llvm/lib/Target/Hexagon/HexagonOperands.td
+1-2llvm/lib/Target/Hexagon/CMakeLists.txt
+46-1584 files

FreeNAS/freenas 0635129 — src/middlewared/middlewared/plugins disk.py

by bugclerk via GitHub on ⎇
NAS-137391 / 25.10-RC.1 / fix disk.query crash on SD card readers (by yocalebo) (#17113)

Original PR: https://github.com/truenas/middleware/pull/17112

---------

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+14-4src/middlewared/middlewared/plugins/disk.py
+14-41 files

LLVM/project e96ff45 — clang/lib/AST/ByteCode InterpState.cpp InterpState.h

by Timm Baeder via GitHub on ⎇
[clang][bytecode] Lazily create DynamicAllocator (#155831)

Due to all the tracking via map(s) and a BumpPtrAllocator, the creating
and destroying the DynamicAllocator is rather expensive. Try to do it
lazily and only create it when first calling
InterpState::getAllocator().
DeltaFile
+7-3clang/lib/AST/ByteCode/InterpState.cpp
+8-2clang/lib/AST/ByteCode/InterpState.h
+15-52 files

LLVM/project bde2abd — clang/lib/Frontend FrontendAction.cpp, clang/test/Modules umbrella_dir_order.m

by Richard Howell via GitHub on ⎇
[clang] load umbrella dir headers in sorted order (#156108)

Clang modules sort the umbrella dir headers by name before adding to the
module's includes to ensure deterministic output across different file
systems.
This is insufficient however, as the header search table is also
serialized.
This includes all the loaded headers by file reference, which are
allocated
incrementally. To ensure stable output we have to also create the file
references in sorted order.
DeltaFile
+21-19clang/lib/Frontend/FrontendAction.cpp
+11-0clang/test/Modules/umbrella_dir_order.m
+3-0clang/test/Modules/Inputs/umbrella_header_order/module.modulemap
+0-0clang/test/Modules/Inputs/umbrella_header_order/umbrella/F.h
+0-0clang/test/Modules/Inputs/umbrella_header_order/umbrella/D.h
+0-0clang/test/Modules/Inputs/umbrella_header_order/umbrella/A.h
+35-193 files not shown
+35-199 files

LLVM/project 8513699 — clang/test/CIR/CodeGenOpenACC loop-reduction-clause-inline-ops.cpp combined-reduction-clause-outline-ops.cpp

by Erich Keane via GitHub on ⎇
[OpenACC] 'reduction' 'one-init' lowering, */&& operators. (#156122)

The * and && operators of a reduction require a starting value of '1'.
This patch implements that by looping through every type and creating an
init-list that puts a 1 in place of every initializer.

This patch will be followed up by a patch that generalizes this, as
`min`, `max`, and `&` all have different initial values.
DeltaFile
+144-8clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
+142-9clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
+143-8clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
+143-8clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
+142-9clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
+142-9clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
+856-5113 files not shown
+1,900-16419 files

FreeNAS/freenas cdd308a — src/middlewared/middlewared/plugins disk.py

by caleb via Bugclerk on ⎇
flake8

(cherry picked from commit 258fb0503945acf87d67a57796d7a7287c8f6b6b)
DeltaFile
+1-1src/middlewared/middlewared/plugins/disk.py
+1-11 files

FreeNAS/freenas 70fc610 — src/middlewared/middlewared/plugins disk.py

by caleb via Bugclerk on ⎇
fix disk.query crash on SD card readers

(cherry picked from commit cd94c19f982c13ef30cb9b8fe2969d6d2e27c5d1)
DeltaFile
+14-4src/middlewared/middlewared/plugins/disk.py
+14-41 files

FreeNAS/freenas 294a283 — src/middlewared/middlewared/plugins disk.py

by Caleb St. John via GitHub on ⎇
NAS-137391 / 26.04 / fix disk.query crash on SD card readers (#17112)
DeltaFile
+14-4src/middlewared/middlewared/plugins/disk.py
+14-41 files

LLVM/project cb80fa7 — llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/X86 bitop-of-castops.ll

by XChy via GitHub on ⎇
[VectorCombine] Support pattern `bitop(bitcast(x), C) -> bitcast(bitop(x, InvC))` (#155216)

Resolves #154797.
This patch adds the fold `bitop(bitcast(x), C) -> bitop(bitcast(x),
cast(InvC)) -> bitcast(bitop(x, InvC))`.
The helper function `getLosslessInvCast` tries to calculate the constant
`InvC`, satisfying `castop(InvC) == C`, and will try its best to keep
the poison-generated flags of the cast operation.
DeltaFile
+160-0llvm/test/Transforms/VectorCombine/X86/bitop-of-castops.ll
+143-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+303-02 files

FreeBSD/ports 6ffc23c — multimedia/plexmediaserver-plexpass distinfo Makefile

by Ben Shertenlieb via Vladimir Druzenko (vvd) on ⎇
multimedia/plexmediaserver-plexpass: Update 1.42.1.10060 => 1.42.2.10102

Changelog:
https://forums.plex.tv/t/plex-media-server/30447/688

PR:     289254
DeltaFile
+3-3multimedia/plexmediaserver-plexpass/distinfo
+2-2multimedia/plexmediaserver-plexpass/Makefile
+5-52 files

FreeBSD/ports 35e9f64 — textproc/py-mkdocs-include-markdown-plugin distinfo Makefile

by Vladyslav Movchan via Vladimir Druzenko (vvd) on ⎇
textproc/py-mkdocs-include-markdown-plugin: Update 7.1.6 => 7.1.7

Changelog:
- Fix passing negative values to `heading-offset` argument of
  `include-markdown` directive.
https://github.com/mondeja/mkdocs-include-markdown-plugin/releases/tag/v7.1.7

PR:     289247
MFH:    2025Q3
(cherry picked from commit 3587fbd0fe60b414c986ade739d2a41f5548b917)
DeltaFile
+3-3textproc/py-mkdocs-include-markdown-plugin/distinfo
+1-1textproc/py-mkdocs-include-markdown-plugin/Makefile
+4-42 files

Illumos/gate 422d8c4 — usr/src/boot/i386/libi386 comconsole.c

by Toomas Soome on ⎇
17286 loader: serial port setup in comconsole is missing env vars
Reviewed by: Hans Rosenfeld <rosenfeld at grumpf.hope-2000.org>
Reviewed by: Dan McDonald <danmcd at edgecast.io>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
DeltaFile
+37-175usr/src/boot/i386/libi386/comconsole.c
+37-1751 files

FreeBSD/ports 3587fbd — textproc/py-mkdocs-include-markdown-plugin distinfo Makefile

by Vladyslav Movchan via Vladimir Druzenko (vvd) on ⎇
textproc/py-mkdocs-include-markdown-plugin: Update 7.1.6 => 7.1.7

Changelog:
- Fix passing negative values to `heading-offset` argument of
  `include-markdown` directive.
https://github.com/mondeja/mkdocs-include-markdown-plugin/releases/tag/v7.1.7

PR:     289247
MFH:    2025Q3
DeltaFile
+3-3textproc/py-mkdocs-include-markdown-plugin/distinfo
+1-1textproc/py-mkdocs-include-markdown-plugin/Makefile
+4-42 files

LLVM/project 1b86547 — llvm/test/CodeGen/AMDGPU si-fold-aligned-vgprs.mir

by Matt Arsenault on ⎇
fix test
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
+2-21 files

LLVM/project 9690466 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

by Matt Arsenault on ⎇
AMDGPU: Refactor isImmOperandLegal

The goal is to expose more variants that can operate without
preconstructed MachineInstrs or MachineOperands.
DeltaFile
+24-14llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+0-7llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+6-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+38-224 files

LLVM/project 8867ca0 — llvm/lib/Target/AMDGPU GCNDPPCombine.cpp

by Matt Arsenault on ⎇
Improve debug printing and add comment
DeltaFile
+9-4llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+9-41 files

LLVM/project 8961a0c — llvm/lib/Target/AMDGPU SIFoldOperands.cpp SIDefines.h, llvm/test/CodeGen/AMDGPU fold-imm-copy-agpr.mir fold-imm-copy.mir

by Matt Arsenault on ⎇
AMDGPU: Fold 64-bit immediate into copy to AV class

This is in preparation for patches which will intoduce more
copies to av registers.
DeltaFile
+34-51llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
+11-15llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
+18-5llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+5-5llvm/lib/Target/AMDGPU/SIDefines.h
+1-5llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+69-815 files

LLVM/project f127217 — llvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp

by Matt Arsenault on ⎇
AMDGPU: Add version of isImmOperandLegal for MCInstrDesc

This avoids the need for a pre-constructed instruction, at least
for the first argument.
DeltaFile
+16-11llvm/lib/Target/AMDGPU/SIInstrInfo.h
+5-6llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+21-172 files

LLVM/project 249e2ec — llvm/lib/Target/AMDGPU SIInstrInfo.cpp

by Matt Arsenault on ⎇
merge exec check
DeltaFile
+1-5llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-51 files