[LSR] Refine equality loop exit replacement
Add coverage for an exit count that reaches the recurrence period.
Simplify cleanup of the replaced comparison.
Assisted-by: TRAE CLI (GPT-5.6-Sol)
[LV] Add VPlan printing tests for induction detection (NFC) (#234562)
Add tests for early-exit loops where the latch value of an induction is
a single-entry phi, as left by the loop rotation just before the
vectorizer, and for an FP induction whose step is an instruction defined
outside the loop.
[VPlan] Print call VPInstructions like IR calls. (#234547)
Print call VPInstructions like IR calls by unifying the logic with
existing intrinsic printing.
rtld: add .cfi_undefined lr to rtld_start.S on powerpc*
Without it, LLVM libunwind doesn't know where to stop when unwinding the
main thread, so it uses a stale LR as the return address and crashes.
Our libunwind doesn't do that since 5866c369e4fd reverted it, but
programs that bundle their own copy, like ClickHouse, are hit by it.
amd64, arm64, i386 and riscv already have the same annotation.
Approved by: jhibbits
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D60740
(cherry picked from commit c4fde87a3236b500246d4fce76dbca2a3d64f73a)
(cherry picked from commit aaa1abfc0ba6b366ef7fe48f70040f3a5b3e6b0c)
powerpc64: give each CPU its own KDB trap stack
Kernel mode program, trace, breakpoint and machine check exceptions go
through dbtrap, which saves the registers on trapstk and, if KDB doesn't
want the trap, restores them from there and continues with the normal
trap handler. There was just one trapstk for all CPUs, so when two of
them trapped at the same time they overwrote each other's frame and one
of them carried on with the other's registers. DTrace fbt probes are
these traps, so a probe on a function that runs on several CPUs at once
took the kernel down within seconds.
Keep the stack in the pcpu instead. The boot CPU gets a static one,
since it's set up before malloc works, the others allocate theirs in
cpu_pcpu_init() like the Book-E critical interrupt stack.
Approved by: jhibbits
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D60362
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tests/sys/kern: stress FP registers across sigreturn on powerpc64
This is the program that found the races fixed in 1f1043d550ea. One
thread keeps a pattern in f14-f31 across a signal, while helpers pinned
to the same CPU keep different patterns in the real registers and get
woken up from another CPU to preempt it at random points. If the kernel
ever hands it somebody else's registers, the pattern doesn't match.
The register loads, the thr_kill() and the handshake with the helper are
in assembly so that nothing touches the FP registers between sigreturn
and the check. It runs for ten seconds and is skipped with fewer than
two CPUs.
Requested by: adrian
Approved by: jhibbits
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D60411
(cherry picked from commit 35a226dded9934c6beb5945a982a705712454be1)
(cherry picked from commit 8d3658947030aedf037e2f7b48c313049eddc7ff)
[CIR] Restrict union tail padding to integers
CIRGen pads a union's tail with !u8i or !cir.array<!u8i x N>, but the
verifier accepted any padding type. Other types broke consumers that
size the union: incomplete-record padding asserted in
computeStructSize, and scalable-vector padding made CallConvLowering
emit a byval of meaningless size.
The verifier now requires the padding to be an integer or an array of
integers. This also covers the earlier void-padding check.
Assisted-by: Claude Code (Claude Opus 5.5)
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Replace NOT followed by merging AND with BIC for expressions such as:
return svand_u32_m(pg, a, svnot_u32_x(pg, b));
Combine when NOT is the second operand and its predicate matches the AND
predicate or is all-active.
Use predicated BIC to preserve the AND's first operand in inactive
lanes. Use unpredicated BIC when the AND predicate is all-active.
Do not commute merging AND operands, since this would change inactive
results. Leave pairs with incompatible predicates unchanged.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Select merging AND-NOT operations with TableGen patterns instead of the C++ combine. Preserve the first operand in inactive lanes and use an unpredicated BIC when both predicates are all-active.
fixup! Replace performSVEAndNotIntrinsicCombine() with tablegen
Move AND_U and NOT matching to TableGen, using a shared pattern fragment
for both operand orders. Retain register and immediate AND selection
for other AND_U operations.
