LLVM/project 5643415clang/test/OpenMP target_codegen.cpp target_simd_codegen.cpp, llvm/include/llvm/Frontend/Offloading Utility.h

[OpenMP] Use ext linkage for kernels handles and globals handles keep… (#202827)

… linkage

Host handles are now emmitted with external linkage to clash if two
kernels with the same name are registered. This could have happen right
now and silently corrupt the program, but it can happen more easily once
we allow users to name their kernels.

In the same patch we make global variable handles retain the linkage of
the global variable, forcing clashes for external ones and continue to
support weak use cases. The exception is common linkage, which we
transform into weak for the entry as there is no zero initialization.
DeltaFile
+11-11clang/test/OpenMP/target_codegen.cpp
+12-6llvm/lib/Frontend/Offloading/Utility.cpp
+8-8clang/test/OpenMP/target_simd_codegen.cpp
+8-8mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
+4-4clang/test/OpenMP/target_indirect_codegen.cpp
+4-4llvm/include/llvm/Frontend/Offloading/Utility.h
+47-4114 files not shown
+75-6820 files

LLVM/project 3a2fbe5lldb/unittests/ObjectFile/MachO MachOTrieTest.cpp

[lldb] Add more Mach-O export trie unit tests (NFC) (#202814)

Extend MachOTrieTest with cases that exercise ParseTrieEntries paths the
existing tests miss, all against the current parser with no functional
change. They cover well-formed edge cases (sibling breadth, empty and
single-character edge labels, large multi-byte addresses, ARM/Thumb and
stub-resolver handling, mixed exports and re-exports) and malformed
input that must be tolerated or rejected without crashing (a shared
subtree, an unterminated edge string, an excessive children count, a
truncated terminalSize, and an out-of-range start offset).

Assisted-by: Claude
DeltaFile
+205-0lldb/unittests/ObjectFile/MachO/MachOTrieTest.cpp
+205-01 files

LLVM/project 91f2a30mlir/include/mlir/Dialect/Linalg/IR LinalgEnums.td, mlir/lib/Dialect/Linalg/IR LinalgOps.cpp

[mlir][linalg] Add inverse triag, log  to elementwise ops (#202786)

Follow up to #200950

Add acos, acosh, asin, asinh, atan, atanh, log10, log1p, log2 to
elementwise ops

These math operations are added as UnaryFn enum cases and supported
through linalg.elementwise only, with no named op definitions. The
specialize pass converts linalg.generic containing these math ops to
linalg.elementwise when emitting category ops

Co-authored-by: Vinit Deodhar <vinitdeodhar at users.noreply.github.com>
DeltaFile
+91-1mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
+45-0mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
+19-1mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
+18-0mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+10-1mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td
+183-35 files

LLVM/project dc2a534clang/test/CIR/CodeGen complex.cpp, clang/test/CIR/CodeGenOpenACC private-clause-pointer-array-recipes-CtorDtor.cpp private-clause-pointer-array-recipes-NoOps.cpp

[CIR] Add custom assembly format for alloca op to fix flag parsing (#198962)

The previously used assembly format was generating code like:
```cpp
  if (::mlir::succeeded(parser.parseOptionalComma())) {
    props.init = parser.getBuilder().getUnitAttr();
    if (parser.parseKeyword("init"))
      return ::mlir::failure();
  }
```
This means that upon seeing any comma, the parser would immediately set
the `init` attribute and then expect the keyword "init" to follow. So a
valid input like `["n", const]` would fail with:
```bash
  error: expected 'init'
```
DeltaFile
+111-111clang/test/CIR/CodeGen/complex.cpp
+104-104clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+82-82clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-NoOps.cpp
+76-76clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
+76-76clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
+76-76clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
+525-525367 files not shown
+4,426-4,416373 files

FreeBSD/ports c642a2adatabases/sabiql distinfo Makefile.crates

databases/sabiql: Update to 1.12.3

ChangeLog:      https://github.com/riii111/sabiql/releases/tag/v1.12.3
Reported by:    riii111 <notifications at github.com>
DeltaFile
+43-27databases/sabiql/distinfo
+20-12databases/sabiql/Makefile.crates
+2-2databases/sabiql/Makefile
+65-413 files

LLVM/project c5c3359compiler-rt/lib/asan CMakeLists.txt

[asan] Fix asan_new_delete.cpp C++ header resolution under -nostdinc++ (#202816)

The COMPILER_RT_ASAN_ENABLE_EXCEPTIONS gate in asan/CMakeLists.txt
enables -fexceptions on the C++ slice (RTAsan_cxx /
RTAsan_dynamic_cxx — asan_new_delete.cpp) and tries to expose C++
standard headers to that TU (for forthcoming std::bad_alloc support)
by stripping -nostdinc++ from its cflags. The strip works for native
standalone builds but is wrong for cross builds: the host C++ headers
aren't valid for the target.

Split the C++-slice flag handling into two paths inside the existing
EXCEPTIONS gate:

  * In-tree libc++ available (TARGET cxx-headers OR HAVE_LIBCXX):
    keep -nostdinc++, append ${COMPILER_RT_CXX_CFLAGS} (a generator
    expression that expands to "-isystem <prepared cxx-headers dir>"),
    and add cxx-headers to DEPS so the header tree is staged before
    the compile. Mirrors the pattern in orc / fuzzer / memprof /
    tsan / xray.

    [10 lines not shown]
DeltaFile
+38-9compiler-rt/lib/asan/CMakeLists.txt
+38-91 files

LLVM/project 3763e42llvm/lib/Support SpecialCaseList.cpp, llvm/unittests/Support SpecialCaseListTest.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+80-15llvm/lib/Support/SpecialCaseList.cpp
+13-3llvm/unittests/Support/SpecialCaseListTest.cpp
+93-182 files

LLVM/project c5ca5c2llvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+30-2llvm/lib/Support/SpecialCaseList.cpp
+30-21 files

LLVM/project 2dac260llvm/lib/Support SpecialCaseList.cpp

rebase

Created using spr 1.3.7
DeltaFile
+6-4llvm/lib/Support/SpecialCaseList.cpp
+6-41 files

LLVM/project e8401b1llvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+4-2llvm/lib/Support/SpecialCaseList.cpp
+4-21 files

LLVM/project 939860eclang/lib/CIR/CodeGen CIRGenAsm.cpp, clang/test/CIR/CodeGen inline-asm.c

[CIR] Fix inline asm operand-attr indexing (#202790)

Inline asm with a register operand ordered before a memory operand, e.g. `asm("" :: "r"(i), "m"(g))`, crashes CIRGen at the `"pointer type expected"` / `"element type differs from pointee type"` assertions in `emitAsmStmt`.

The element-type-attribute loop walks `argElemTypes` with a counter that only advances on entries that have an element type, but uses that counter to index the parallel `args` array. The two arrays are the same length (every operand pushes to both, and `assert(args.size() == operandAttrs.size())` enforces it), so the matching value for `argElemTypes[k]` is `args[k]`. As soon as a register operand (null element type) precedes a memory operand (non-null), the counter desyncs and reads the wrong operand — a non-pointer, or a pointer with the wrong pointee.

The fix indexes `args` positionally with `llvm::enumerate`, matching classic CodeGen in `CGStmt.cpp`, which iterates `llvm::enumerate(ArgElemTypes)` and attaches the element-type attribute at `Pair.index()`. New `t35` in `inline-asm.c` covers the register-before-memory ordering and checks the lowered IR against classic codegen.
DeltaFile
+20-0clang/test/CIR/CodeGen/inline-asm.c
+2-3clang/lib/CIR/CodeGen/CIRGenAsm.cpp
+22-32 files

LLVM/project 7799b76llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.set.inactive.chain.arg.ll amdgpu-cs-chain-cc.ll

AMDGPU/GlobalISel: RegBankLegalize rules for set_inactive intrinsics
DeltaFile
+103-119llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
+49-41llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
+38-35llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-2llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
+202-2011 files not shown
+204-2037 files

LLVM/project 06cc1bacompiler-rt/lib/lsan lsan_common.cpp

lsan: Document that ptrace_scope needs to be disabled.

As far as I'm aware, this is the reason why
http://45.33.8.238/linux/201640/step_9.txt is failing.

Reviewers: vitalybuka

Pull Request: https://github.com/llvm/llvm-project/pull/202838
DeltaFile
+3-0compiler-rt/lib/lsan/lsan_common.cpp
+3-01 files

LLVM/project e1abcb0clang/lib/CodeGen CodeGenFunction.h

[clang] restore Alloca from CreateAggTemp (#202978)

Noticed in post-review feedback on #200427
DeltaFile
+1-3clang/lib/CodeGen/CodeGenFunction.h
+1-31 files

LLVM/project cb78ee9llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU isel-whole-wave-functions.ll whole-wave-functions.ll

AMDGPU/GlobalISel: RegBankLegalize rules for WHOLE_WAVE_FUNC setup and return (#203001)
DeltaFile
+16-11llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-2llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+1-1llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
+24-144 files

LLVM/project 826a484flang/lib/Semantics check-omp-structure.cpp check-omp-structure.h

[flang][OpenMP] Remove CheckSymbolName{,s}, NFC (#202811)

These functions checked if each OmpObject had a symbol, and emitted a
diagnostic if not. Name not having a symbol is an internal compiler
error (which will be detected separately), and not something actionable
for the user.

Remove these functions since they don't serve any purpose anymore.
DeltaFile
+1-38flang/lib/Semantics/check-omp-structure.cpp
+0-4flang/lib/Semantics/check-omp-structure.h
+1-422 files

NetBSD/src CjBjaWDshare/man/man4/man4.evbarm awge.4

   awge(4): minor tweaks

   Move the list of authors to the AUTHORS section.
   In bibliographic refs .%A is for human authors, corporations are .%Q
VersionDeltaFile
1.4+8-11share/man/man4/man4.evbarm/awge.4
+8-111 files

FreeBSD/ports 0743aecnet-im/py-zapzap distinfo Makefile

net-im/py-zapzap: Update to 6.5.1

ChangeLog:

- https://github.com/rafatosta/zapzap/releases/tag/6.5
- https://github.com/rafatosta/zapzap/releases/tag/6.5.1

Reported by:    Rafael Tosta <notifications at github.com>
DeltaFile
+3-3net-im/py-zapzap/distinfo
+1-1net-im/py-zapzap/Makefile
+4-42 files

LLVM/project f30f721lldb/test/API/commands/frame/var-dil/expr/Assignment TestFrameVarDILAssign.py

[LLDB] Update DIL assignment test to not break on arm-32. (#203007)

Test included a case that was not valid on arm-32. This removes that
case.
DeltaFile
+0-1lldb/test/API/commands/frame/var-dil/expr/Assignment/TestFrameVarDILAssign.py
+0-11 files

Dreckly/dreckly a9910d0www/palemoon distinfo Makefile.common

palemoon: Update to 34.3.0.1
DeltaFile
+9-9www/palemoon/distinfo
+2-2www/palemoon/Makefile.common
+11-112 files

XigmaNAS/svn 10651trunk/etc/inc/gui document.php

use array_last(), new since PHP 8.5
DeltaFile
+1-1trunk/etc/inc/gui/document.php
+1-11 files

LLVM/project 9054589llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-load-i8-stride-8.ll

[X86] combineTargetShuffle - fold vpermv3(widen(x),mask,widen(y)) -> vpermv(widen(concat(x,y)),mask') (#203031)

We already handle the case where the src vectors were half size, but we
can generalize this to widening from xmm to zmm as well - mainly to help
non-VLX builds

A couple of codesize increases in non-VLX builds - mostly from
additional asm / kill comments, but also due to a couple of poor folds
in combineConcatVectorOps that need further yak shaving.
DeltaFile
+1,962-1,920llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,166-1,460llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+322-308llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+176-204llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
+80-92llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
+13-7llvm/lib/Target/X86/X86ISelLowering.cpp
+3,719-3,9912 files not shown
+3,733-4,0068 files

NetBSD/src QqdJfi0usr.bin/m4 main.c

   map debugfile to 'o'
VersionDeltaFile
1.51+3-3usr.bin/m4/main.c
+3-31 files

Dreckly/dreckly ef3ba15multimedia/ffmpeg6 distinfo Makefile.common

ffmpeg6: Update to 6.1.5
DeltaFile
+3-3multimedia/ffmpeg6/distinfo
+1-1multimedia/ffmpeg6/Makefile.common
+4-42 files

XigmaNAS/svn 10650trunk/etc/inc/filechooser filechooser.php

backtick operator will be deprecated in PHP 8.5
DeltaFile
+32-27trunk/etc/inc/filechooser/filechooser.php
+32-271 files

FreeBSD/ports 8fb5b8cdevel/toomanycooks Makefile pkg-plist, devel/toomanycooks/files patch-cmake_tmc-install.cmake

devel/toomanycooks: do not install a license file (+)

... to a wrong location.

Bump PORTREVISION.

Sponsored by:   tipi.work
DeltaFile
+13-0devel/toomanycooks/files/patch-cmake_tmc-install.cmake
+1-0devel/toomanycooks/Makefile
+0-1devel/toomanycooks/pkg-plist
+14-13 files

NetBSD/pkgsrc-wip acf5eca. Makefile, bftpd Makefile COMMIT_MSG

net/bftpd: Update to version 6.6
DeltaFile
+47-0bftpd/Makefile
+33-0bftpd/COMMIT_MSG
+11-0bftpd/DESCR
+5-0bftpd/distinfo
+4-0bftpd/PLIST
+1-0Makefile
+101-06 files

LLVM/project ebcb4cellvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.ballot.i64.wave32.ll

[AMDGPU][GISel] Handle G_AMDGPU_COPY_VCC_SCC in isLaneMaskFromSameBlock (#202923)

This avoids generating some redundant ANDs with exec.

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+8-32llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
+6-18llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+4-3llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
+24-566 files

FreeBSD/ports 00f77d1net/nats-surveyor distinfo Makefile

net/nats-surveyor: Update to 0.9.10
DeltaFile
+7-7net/nats-surveyor/distinfo
+1-2net/nats-surveyor/Makefile
+8-92 files

FreeBSD/ports a89746bnet/nats-nsc distinfo Makefile

net/nats-nsc: Update to 2.15.0
DeltaFile
+5-5net/nats-nsc/distinfo
+1-2net/nats-nsc/Makefile
+6-72 files