[CIR] Rewrap the x86_64 classifier bridge comment
This paragraph lost its shape over a couple of merges and ended up with
a short orphaned line in the middle. Rewrapping the whole block lets
classifyX86_64Function land mid-line so the lines fill evenly. The
wording is untouched, only the line breaks moved.
Assisted-by: Cursor / claude-opus-5
[MLIR][ODS] Print prop-dict fields with custom printers
Generate a key-value prop-dict printer that dispatches each field to its ODS
printer while retaining attribute conversion for non-compositional default
parsers.
Keep operation-specific property printer hooks ahead of the generated
implementation and preserve legacy input compatibility.
Update the OpenACC cache checks for the generated custom property spelling.
Assisted-by: Codex
[flang][nfc] Split out the pre- and post-cfg FIR pipelines (#218778)
Split the FIR optimization pipeline in its pre- and post-cfg parts and
expose the builders so that alternative downstream pipelines can build
around them.
[MLIR][ODS] Parse prop-dict fields with custom parsers (#218798)
Teach generated operation parsers to accept a key-value spelling for
prop-dict and dispatch known fields through their ODS parsers. Keep the
DictionaryAttr spelling as a compatibility path and use attribute
conversion when a property has no usable FieldParser.
Reland #217590 after fixing the MSAN specific failure: the
`FieldParser<SmallVector<int32_t>>` specialization collided with a
generic instantiation in another translation unit. Under MSan, the
linker selected the generic parser instead of the specialization.
See #155475
Assisted-by: Codex
[BOLT] Skip data-hole filling unless data reordering is enabled (#214893)
BinaryContext::postProcessSymbolTable unconditionally called
fixBinaryDataHoles(), which walks every allocatable section and, for
each gap in its address space, either grows a zero-sized data symbol or
creates a synthetic "HOLEat" BinaryData (plus an MCSymbol and
GlobalSymbols/BinaryDataMap entries). This machinery was introduced
(0e4d86bf, 2017) for one purpose: to give static data reordering
(-reorder-data) a movable object covering every byte of a section. It
has no other consumer.
On a large binary, these synthetic objects are live from
buildFunctionsCFG through the end of the run and, at the RSS peak
(during debug info rewriting), fixBinaryDataHoles accounted for 1669 MB
(~1-2%) of peak RSS -- memory spent entirely for a feature that is off
by default.
Gate fixBinaryDataHoles() (and the zero-sized-symbol validation loop
that presumes it ran) on a non-empty opts::ReorderData, keeping
generateSymbolHashes() unconditional.
Stop shipping /etc/wall_cmos_clock in the image
The file makes the kernel read the RTC as local time, so the clock is
off by one UTC offset on any machine whose RTC keeps UTC. That applied
to the live session and to every install, since the install is a cpdup
of the live system and nothing in the installer revisited the file.
pc-sysinstall now creates or removes it from the utcClock= config key,
so the image no longer has to pick a side, and the live session gets a
correct clock while the installer is running. Machines that really do
keep local time in the RTC, which in practice means dual-booting
Windows, are handled by the installer front-end instead.
Resolves: ghostbsd/issues#390
cpuctl(8): decode L2 cache associativity for VIA CPUs using the AMD cache lookup
table for the 0x80000006 CPUID function associativity value.
Use `cpuid leaf 4' to get cache parameters for Zhaoxin and late VIA CPU models.
Mirrors the changes from identcpu.c rev. 1.142.
Additionally, use via_cpu_probe() and via_cpu_cacheinfo() for CPUVENDOR_IDT
family > 6 CPUs to identify Zhaoxin CPUs and their features.
Also, print feature 5-7 bits for CPUVENDOR_IDT, which appear to be compatible
with Intel.
Use vendorname = "Zhaoxin" for family 7 models.
Tested on various 32-bit and 64-bit VIA and Zhaoxin CPUs
(Samuel 2 / Nehemiah, Esther (32-bit), multiple Nano models, and KX-U6580/7000).
PR kern/60619
pullups needed to netbsd-11 and netbsd-10.
[3/3][RegAlloc][LiveRegMatrix] Added validity check between VRM and LRM. (#197778)
Check that every VRM-assigned vreg with a non-empty live interval must
have its segments in the Matrix for its assigned physical reg.
Depends on https://github.com/llvm/llvm-project/pull/197773 and
https://github.com/llvm/llvm-project/pull/197776. While there are no
source conflicts, adding this verification without the other 2 patches
would make the following LIT tests fail.
CodeGen/X86/AMX/amx-gemm.ll
CodeGen/X86/apx/push2-pop2.ll
CodeGen/X86/udivmodei5.ll
CodeGen/X86/apx/pr191368.ll
Assisted-by: Cursor/Claude Opus
