LLVM/project e4dded4llvm/test/CodeGen/SPIRV/hlsl-resources CalculateLevelOfDetail.ll

Fix up test.
DeltaFile
+2-5llvm/test/CodeGen/SPIRV/hlsl-resources/CalculateLevelOfDetail.ll
+2-51 files

LLVM/project 4380ae6flang-rt CMakeLists.txt, flang-rt/lib CMakeLists.txt

[Flang-RT] Support building no library (#187868)

Allow setting both FLANG_RT_ENABLE_SHARED and FLANG_RT_ENABLE_STATIC to
OFF at the same time.

This is extracted out of #171515 to make that PR a little smaller. By
itself it makes little sense since if not building either the `.a` or
the `.so`, you are not building anything. But with #171515, the module
files are still built, allowing building the modules files without the
library. This is mostly intended for GPGPU targets where building the
library is not always needed, but the module files are.
DeltaFile
+29-23flang-rt/lib/runtime/CMakeLists.txt
+16-11flang-rt/CMakeLists.txt
+10-5flang-rt/lib/CMakeLists.txt
+55-393 files

FreeNAS/freenas d238a88src/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/plugins/zfs snapshot_hold_release_impl.py

NAS-140367 / 27.0.0-BETA.1 / Allow the trains to be marked as unstable to make "the system can be upgraded only to the next train" constraint feasible (by themylogin) (by bugclerk) (#18564)

Original PR: https://github.com/truenas/middleware/pull/18541

---------

Co-authored-by: themylogin <themylogin at gmail.com>
DeltaFile
+62-3src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+35-8src/middlewared/middlewared/plugins/update_/trains.py
+2-0src/middlewared/middlewared/plugins/zfs/snapshot_hold_release_impl.py
+99-113 files

LLVM/project 61533e7llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[TargetLowering] Update comments for prepareUREMEqFold to show non-zero comparison constants are allowed. NFC (#188550)
DeltaFile
+4-3llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+4-31 files

LLVM/project 339315dllvm/lib/Transforms/AggressiveInstCombine AggressiveInstCombine.cpp

[AggressiveInstCombine] Use APInt::getOneBitSet. NFC (#188545)
DeltaFile
+2-1llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+2-11 files

LLVM/project 4a352bbllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[TargetLowering] Use APInt::abs in prepareSREMEqFold. NFC (#188551)
DeltaFile
+2-3llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+2-31 files

LLVM/project 0205e8cclang/lib/Sema HLSLBuiltinTypeDeclBuilder.cpp

Add missing include.
DeltaFile
+1-0clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+1-01 files

LLVM/project a546c77clang/lib/Headers/hlsl hlsl_alias_intrinsics.h, clang/test/CodeGenHLSL/builtins QuadReadAcrossY.hlsl

[HLSL][DXIL][SPIRV] QuadReadAcrossY intrinsic support (#187440)

This PR adds QuadReadAcrossY intrinsic support in HLSL with codegen for
both DirectX and SPIRV backends. Resolves
https://github.com/llvm/llvm-project/issues/99176.

- [x] Implement `QuadReadAcrossY` clang builtin,
- [x] Link `QuadReadAcrossY` clang builtin with `hlsl_intrinsics.h`
- [x] Add sema checks for `QuadReadAcrossY` to
`CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp`
- [x] Add codegen for `QuadReadAcrossY` to `EmitHLSLBuiltinExpr` in
`CGBuiltin.cpp`
- [x] Add codegen tests to
`clang/test/CodeGenHLSL/builtins/QuadReadAcrossY.hlsl`
- [x] Add sema tests to
`clang/test/SemaHLSL/BuiltIns/QuadReadAcrossY-errors.hlsl`
- [x] Create the `int_dx_QuadReadAcrossY` intrinsic in
`IntrinsicsDirectX.td`
- [x] Create the `DXILOpMapping` of `int_dx_QuadReadAcrossY` to `123` in

    [9 lines not shown]
DeltaFile
+171-0clang/test/CodeGenHLSL/builtins/QuadReadAcrossY.hlsl
+99-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+87-0llvm/test/CodeGen/DirectX/QuadReadAcrossY.ll
+44-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/QuadReadAcrossY.ll
+28-0clang/test/SemaHLSL/BuiltIns/QuadReadAcrossY-errors.hlsl
+7-0llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
+436-010 files not shown
+463-116 files

pfSense/pfsense 9b2b1cftools/conf/pfPorts poudriere_bulk

Remove lsof temporarily until it is updated after upstream changes

https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=294023
DeltaFile
+0-1tools/conf/pfPorts/poudriere_bulk
+0-11 files

LLVM/project fe10ca4flang/lib/Lower/OpenMP DataSharingProcessor.cpp, flang/test/Lower/OpenMP distribute-parallel-do-simd.f90 composite_simd_linear.f90

Revert "Reland "[flang][OpenMP] Fix lowering of LINEAR iteration variables (#183794)" (#187766)" (#188560)

This reverts commit 7af471a8eda3e1882657115d36eb000df3ffa5fd.

Fixes #188536
DeltaFile
+13-12flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
+12-13flang/test/Lower/OpenMP/composite_simd_linear.f90
+5-8flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
+5-5flang/test/Lower/OpenMP/loop-pointer-variable.f90
+5-5flang/test/Lower/OpenMP/wsloop-simd.f90
+3-3flang/test/Lower/OpenMP/distribute-simd.f90
+43-463 files not shown
+48-549 files

LLVM/project 7006fa0mlir/test/Dialect/Linalg tile-and-fuse-tensors.mlir, mlir/test/lib/Dialect/Linalg TestLinalgFusionTransforms.cpp

[mlir][linalg] Fix crash in greedy fusion when producer is fused into multiple consumers (#188561)

When the same producer is fused into multiple consumers in
fuseLinalgOpsGreedily, the second fusion can't find the original op in
the linalgOps vector (already replaced by the first fusion). llvm::find
returns end(), and writing to *end() caused an out-of-bounds stack write
that corrupted the adjacent OpBuilder's context pointer, leading to a
crash.

Fix by checking that find() returned a valid iterator before updating.

Fixes #122247

Assisted-by: Claude Code
DeltaFile
+37-0mlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
+2-1mlir/test/lib/Dialect/Linalg/TestLinalgFusionTransforms.cpp
+39-12 files

FreeBSD/ports d3f22fbcad Makefile, cad/route-rnd Makefile pkg-descr

cad/route-rnd: [NEW PORT] Flexible, modular autorouter for Printed Circuit Boards

route-rnd is a Free Software flexible, modular autorouter for Printed Circuit
Boards

- modular, supports different routing algorithms
- fits well in a UNIXy workflow
- the designed-for-simplicity file format makes it easy to interface
- fully CLI, no GUI required
- active development, frequent releases
- Free Software license (GNU GPLv2+)

WWW: http://www.repo.hu/projects/route-rnd/

Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+33-0cad/route-rnd/Makefile
+9-0cad/route-rnd/pkg-descr
+3-0cad/route-rnd/distinfo
+1-0cad/Makefile
+46-04 files

LLVM/project 4330de5clang/test/TableGen hlsl-intrinsics.td, clang/utils/TableGen HLSLEmitter.cpp

Merge branch 'main' into users/s-perron/texture2d-mips
DeltaFile
+258-592llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+752-0llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll
+590-0clang/utils/TableGen/HLSLEmitter.cpp
+574-9llvm/unittests/ADT/PointerUnionTest.cpp
+132-389llvm/include/llvm/CodeGenTypes/LowLevelType.h
+469-0clang/test/TableGen/hlsl-intrinsics.td
+2,775-990722 files not shown
+17,397-8,444728 files

LLVM/project 212cbefflang/lib/Lower/OpenMP DataSharingProcessor.cpp

[flang] Fix unused variable error (NFC) (#188358)
DeltaFile
+1-2flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
+1-21 files

LLVM/project 69974d5mlir/lib/Transforms Mem2Reg.cpp

[MLIR] [Mem2Reg] Quick fix for dominance info invalidation (#188518)

We have identified a problem with DominanceInfo caching in Mem2Reg. It
appears to also be subject to incorrect cache hits when regions are
deleted, causing sporadic bugs that are difficult to test for.

This quick fix invalidates region that could be invalidated. This
attempts to not be too eager by only invalidating regions that are
exposed to a `finalizePromotion` call.

Ultimately it would be nice to have the ability to move the cached
information from one region to the next, but this is currently not
supported by DominanceInfo.

I was not able to produce a test for this as it is very sporadic. We
would need to be testing for a case where a region is re-allocated at
the same address as a previously erased region. If you know how to make
this sort of behavior consistent, I would be interested. Otherwise this
might require no testing.
DeltaFile
+7-0mlir/lib/Transforms/Mem2Reg.cpp
+7-01 files

LLVM/project ecb89afclang/lib/Sema HLSLBuiltinTypeDeclBuilder.cpp

Add assert
DeltaFile
+1-0clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+1-01 files

LLVM/project b492b55libclc/clc/lib/generic/math clc_flush_if_daz.inc

libclc: clspv does not need workaround for flush_if_daz (#188555)
DeltaFile
+1-1libclc/clc/lib/generic/math/clc_flush_if_daz.inc
+1-11 files

FreeNAS/freenas 6dae4c5src/middlewared/middlewared/plugins/pool_ dataset_details.py

Fix failing to load datasets

(cherry picked from commit a6884be8ea2f7edf9c43f2a5c978cfa901ab2e3c)
DeltaFile
+3-5src/middlewared/middlewared/plugins/pool_/dataset_details.py
+3-51 files

FreeNAS/freenas 4b92b1fsrc/middlewared/middlewared/plugins/pool_ dataset_details.py

Fix failing to load datasets

(cherry picked from commit a6884be8ea2f7edf9c43f2a5c978cfa901ab2e3c)
DeltaFile
+3-5src/middlewared/middlewared/plugins/pool_/dataset_details.py
+3-51 files

FreeNAS/freenas 7e30f94src/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/pytest/unit/plugins/update test_trains.py

Allow the trains to be marked as unstable to make "the system can be upgraded only to the next train" constraint feasible

(cherry picked from commit 2dd3ed5551ec1efd4a05c985bd96ea49c9b6141c)
(cherry picked from commit cff4796a1a8a0a119206cd0e684fd7eeb5d119b2)
DeltaFile
+35-0src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+13-7src/middlewared/middlewared/plugins/update_/trains.py
+48-72 files

FreeNAS/freenas 7ac687csrc/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/plugins/zfs snapshot_hold_release_impl.py

Avoid checking unnecessary trains

(cherry picked from commit 211c0cd4f76638ba0061a4ef7eda9dd48a488fb2)
(cherry picked from commit dcb6184581ebe8cc3719e41cfeac291d855bf7d4)
DeltaFile
+36-12src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+25-4src/middlewared/middlewared/plugins/update_/trains.py
+2-0src/middlewared/middlewared/plugins/zfs/snapshot_hold_release_impl.py
+63-163 files

FreeNAS/freenas 0aa3cfdsrc/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/pytest/unit/plugins/update test_trains.py

Allow the trains to be marked as unstable to make "the system can be upgraded only to the next train" constraint feasible

(cherry picked from commit 2dd3ed5551ec1efd4a05c985bd96ea49c9b6141c)
(cherry picked from commit cff4796a1a8a0a119206cd0e684fd7eeb5d119b2)
DeltaFile
+35-0src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+13-7src/middlewared/middlewared/plugins/update_/trains.py
+48-72 files

FreeNAS/freenas f5b9294src/middlewared/middlewared/plugins/pool_ dataset_details.py

NAS-140389 / 27.0.0-BETA.1 / Fix failing to load datasets (#18562)
DeltaFile
+3-5src/middlewared/middlewared/plugins/pool_/dataset_details.py
+3-51 files

FreeNAS/freenas 6e3adb4src/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/plugins/zfs snapshot_hold_release_impl.py

Avoid checking unnecessary trains

(cherry picked from commit 211c0cd4f76638ba0061a4ef7eda9dd48a488fb2)
(cherry picked from commit dcb6184581ebe8cc3719e41cfeac291d855bf7d4)
DeltaFile
+36-12src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+25-4src/middlewared/middlewared/plugins/update_/trains.py
+2-0src/middlewared/middlewared/plugins/zfs/snapshot_hold_release_impl.py
+63-163 files

FreeNAS/freenas 812a9e0src/middlewared/middlewared/api/v26_0_0 cloud_sync_providers.py

NAS-140383 / 26.0.0-BETA.2 / Fix cloud sync with S3 provider behind a proxy (by themylogin) (#18545)

Automatic cherry-pick failed. Please resolve conflicts by running:

    git reset --hard HEAD~1
    git cherry-pick -x eb523d8632a47808771d9d50a221c7cd759e9809

If the original PR was merged via a squash, you can just cherry-pick the
squashed commit:

    git reset --hard HEAD~1
    git cherry-pick -x c040b2c73eca807c505645133085226df2c395be

Rclone v1.73 (using AWS SDK v2) signs the Accept-Encoding: identity
header as part of the SigV4 signature. Some reverse proxies modify that
header before it reaches the S3 gateway, so the server computes a
different signature and rejects the request. Setting
sign_accept_encoding = false excludes that header from the signature,
matching what the old rclone v1.67 did.

    [3 lines not shown]
DeltaFile
+3-0src/middlewared/middlewared/api/v26_0_0/cloud_sync_providers.py
+3-01 files

FreeNAS/freenas 3a136d9src/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/plugins/zfs snapshot_hold_release_impl.py

NAS-140367 / 26.0.0-BETA.1 / Allow the trains to be marked as unstable to make "the system can be upgraded only to the next train" constraint feasible (by themylogin) (#18541)

Automatic cherry-pick failed. Please resolve conflicts by running:

    git reset --hard HEAD~1
    git cherry-pick -x 2dd3ed5551ec1efd4a05c985bd96ea49c9b6141c
    git cherry-pick -x 211c0cd4f76638ba0061a4ef7eda9dd48a488fb2

If the original PR was merged via a squash, you can just cherry-pick the
squashed commit:

    git reset --hard HEAD~1
    git cherry-pick -x 054225c3112f4a19eebcee0279801d2b058511ca

The update design says that "the system can be upgraded only to the next
train". This constraint turned out to be too strict.

Currently, the trains are as follows
```

    [69 lines not shown]
DeltaFile
+62-3src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+35-8src/middlewared/middlewared/plugins/update_/trains.py
+2-0src/middlewared/middlewared/plugins/zfs/snapshot_hold_release_impl.py
+99-113 files

LLVM/project 507f697llvm/include/llvm/Transforms/IPO SampleProfileMatcher.h, llvm/include/llvm/Transforms/Utils SampleProfileLoaderBaseImpl.h

[SampleFDO] Check pseudo probe descriptors for unused profile in stale profile matching (#179997)

If a function is fully optimized away in pre-link, it won't show up in
`SymbolMap` in post-link and the check of unused profile would treat it
as unused and allow it to be matched with unrelated functions. Extend
the check to cover such case in post link.
 
Also make `FuncToProfileNameMap` a MapVector so that we always get the
same iterator sequence out of it in `UpdateWithSalvagedProfiles`.
DeltaFile
+76-0llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-unused-probe-desc.ll
+12-2llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+7-0llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-unused-probe-desc.prof
+2-1llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
+2-1llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
+99-45 files

LLVM/project 85049fcclang/lib/CodeGen CGDebugInfo.cpp, clang/test/CodeGenHLSL/debug source-language.hlsl

[HLSL][SPIRV] Add support for -g to generate NonSemantic Debug Info (#187051)

This adds two related changes to HLSL debug info support in the SPIR-V
backend. It's a first small step towards the plan I described in
https://discourse.llvm.org/t/hlsl-spirv-nsdi-debug-info-support-for-clang-dxc/90149.

## Tag HLSL shaders with `DW_LANG_HLSL` in the front-end

`GetSourceLanguage()` in `clang/lib/CodeGen/CGDebugInfo.cpp` checked
`LO.CPlusPlus` before `LO.HLSL`. Since HLSL is compiled as C++, the HLSL
check was never reached. Shaders compiled with `-g` were tagged with
`DW_LANG_C_plus_plus_14` instead of `DW_LANG_HLSL`. The NSDI pass
already had the correct mapping for `DW_LANG_HLSL` but it was never
triggered.

This fixes #136929 and #136995.

## Make `SPIRVEmitNonSemanticDI` activate automatically when `-g` is
used

    [43 lines not shown]
DeltaFile
+34-0clang/test/CodeGenHLSL/debug/source-language.hlsl
+32-0llvm/test/CodeGen/SPIRV/debug-info/hlsl-debug-info-auto-activation.ll
+6-5llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+6-2clang/lib/CodeGen/CGDebugInfo.cpp
+5-3llvm/docs/SPIRVUsage.rst
+2-2llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
+85-124 files not shown
+90-1510 files

LLVM/project 8dd60c0mlir/lib/Dialect/Linalg/IR LinalgOps.cpp, mlir/test/Dialect/Linalg invalid.mlir

[mlir][linalg] Improve inner tile size mismatch diagnostics in pack/unpack verifier (#188525)

Refactor the tile-size consistency check in
`commonVerifierPackAndUnPackOp` from a bulk `all_of` into an indexed
loop so that error messages include the offending dimension index and
the conflicting values, making failures easier to diagnose.

Before:
  error: mismatch in inner tile sizes specified and shaped of tiled
         dimension in the packed type

After (static/static mismatch):
  error: mismatch in inner tile sizes specified and shaped of tiled
         dimension in the packed type at index 1: got 8 \!= 4

After (dynamic tile, static packed dim):
  error: mismatch in inner tile sizes specified at index 1: got static
         shape 8 but dynamic tile size


    [3 lines not shown]
DeltaFile
+21-19mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+6-6mlir/test/Dialect/Linalg/invalid.mlir
+27-252 files

FreeNAS/freenas a6884besrc/middlewared/middlewared/plugins/pool_ dataset_details.py

Fix failing to load datasets
DeltaFile
+3-5src/middlewared/middlewared/plugins/pool_/dataset_details.py
+3-51 files