LLVM/project 5710e41cross-project-tests lit.site.cfg.py.in, cross-project-tests/dtlto path.test

[DTLTO][Windows] Expand short 8.3 form paths in ThinLTO module IDs (#178303)

Windows supports short 8.3 form filenames (e.g. `compile_commands.json`
-> `COMPIL~1.JSO`) for legacy reasons. See:
https://learn.microsoft.com/en-us/windows/win32/fileio/naming-a-file#short-vs-long-names.

Short 8.3 form paths are undesirable in distributed compilation
scenarios because they are local mappings tied to a specific directory
layout on a specific machine. As a result, they can break or defeat
sandboxing and path-based isolation mechanisms used by distributed build
systems.

We have observed such failures with DTLTO even in simple scenarios. For
example, on Windows, running:

```
clang.exe hello.c -flto=thin -fuse-ld=lld -fthinlto-distributor=fastbuild.exe -###
```


    [29 lines not shown]
DeltaFile
+92-0cross-project-tests/dtlto/path.test
+59-9llvm/lib/DTLTO/DTLTO.cpp
+14-1cross-project-tests/lit.site.cfg.py.in
+6-1llvm/include/llvm/DTLTO/DTLTO.h
+171-114 files

LLVM/project 524ae2fmlir/include/mlir/Dialect/Linalg/IR LinalgInterfaces.h, mlir/lib/Dialect/Linalg/IR LinalgInterfaces.cpp

[mlir][linalg] Make conv dim inference return pairing (outputImage, filterLoop) (#180859)

The original method sorts all the dimensions which loses the information
about pairing. It makes other transformation that works on generic op
form harder. The revision ensures the pairing, so callers have more
useful information when they work on transformations.

---------

Signed-off-by: hanhanW <hanhan0912 at gmail.com>
DeltaFile
+173-0mlir/unittests/Dialect/Linalg/InferConvolutionDimsTest.cpp
+26-10mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
+11-0mlir/unittests/Dialect/Linalg/CMakeLists.txt
+6-2mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
+1-0mlir/unittests/Dialect/CMakeLists.txt
+217-125 files

NetBSD/pkgsrc-wip 43fd4a9emacs-git PLIST

emacs-git: add more to PLIST
DeltaFile
+2-0emacs-git/PLIST
+2-01 files

LLVM/project fc64868llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 vec_list_bias_external_insert_shuffled.ll vec_list_bias-inseltpoison.ll

[SLP]Add external uses estimations into tree throttling

Added basic estimations for the external uses, when calculating the cost
of the non-profitable trees. Excluding stores/insertelement, as thay are
very good candidates for the vectorization. Also, tuned
buildvector/gather cost with minimum bitwidth analysis data.

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/178024
DeltaFile
+111-26llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+12-14llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
+12-13llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
+12-13llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
+2-1llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
+149-675 files

LLVM/project da6e301lldb/tools/lldb-dap EventHelper.cpp

[lldb-dap] Adjusting multi-stopped event order. (#181001)

When multiple stopped events are detected we should send the
`"allThreadsStopped":true` last.

Currently, if there are multiple stopped threads and we attempt to step
around the 'allThreadsStopped' ends up with multiple stops highlighted
in the UI.

Reporting the focused thread last fixes this while still correctly
updating the thread state of all stopped threads.

This fixes an issue reported in
https://github.com/llvm/llvm-project/pull/176273#discussion_r2775979486
DeltaFile
+29-17lldb/tools/lldb-dap/EventHelper.cpp
+29-171 files

LLVM/project 0deb1b6offload/plugins-nextgen/level_zero/src L0DynWrapper.cpp

[Offload] Try to load Level Zero loader with version suffix (#180042)

The default Level Zero loader `libze_loader.so` may not be available on
systems that don't have Level Zero development package. Level Zero
loaders with major version suffix are searched in that case.
DeltaFile
+28-2offload/plugins-nextgen/level_zero/src/L0DynWrapper.cpp
+28-21 files

FreeNAS/freenas d4b5bcfsrc/middlewared/middlewared/plugins auth.py, src/middlewared/middlewared/utils/account authenticator.py utmp.py

Remove python-pam and plumb in pam_truenas

This commit removes the python-pam Python library dependency from
TrueNAS middleware and replaces it with truenas_pypam. The most
significant change is the migration of API key authentication from
simple PBKDF2 password hashing to SCRAM-SHA512 (Salted Challenge
Response Authentication Mechanism) as defined in RFC5802. SCRAM is an
authentication protocol that uses PBKDF2-HMAC-SHA512 for key
derivation. API keys are now stored with SCRAM-derived credentials
including salt, stored_key, server_key, and iteration count fields in
the database. A database migration automatically converts existing
PBKDF2-hashed API keys to SCRAM format transparently—existing API keys
will continue to work without requiring regeneration. The commit adds a
new SCRAM authentication mechanism for challenge-response authentication
with replay resistance and mutual validation capabilities, while
maintaining the existing API_KEY_PLAIN mechanism for simple
authentication.

The refactoring includes comprehensive changes to the authentication

    [10 lines not shown]
DeltaFile
+382-507src/middlewared/middlewared/utils/account/authenticator.py
+230-233tests/unit/test_utmp.py
+0-397src/middlewared/middlewared/utils/account/utmp.py
+0-358tests/unit/test_pam_tdb.py
+211-127src/middlewared/middlewared/plugins/auth.py
+56-113src/middlewared/middlewared/utils/account/faillock.py
+879-1,73536 files not shown
+1,592-2,20242 files

NetBSD/pkgsrc-wip b6da670i3blocks Makefile DESCR, i3blocks/patches patch-sys.c

i3blocks: add package

Builds, untested.
DeltaFile
+21-0i3blocks/Makefile
+18-0i3blocks/patches/patch-sys.c
+13-0i3blocks/DESCR
+6-0i3blocks/distinfo
+5-0i3blocks/PLIST
+3-0i3blocks/TODO
+66-01 files not shown
+67-07 files

LLVM/project 1919b3bllvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp, llvm/test/CodeGen/SPIRV single-element-vector.ll

[SPIRV] Scalarize single-element vectors in type creation (#180735)

SPIR-V requires vectors to have at least 2 components. So treat <1 x T>
as T.

Fixes: https://github.com/llvm/llvm-project/issues/171175
DeltaFile
+53-0llvm/test/CodeGen/SPIRV/single-element-vector.ll
+6-0llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+59-02 files

FreeNAS/freenas c3f86c6src/middlewared/middlewared/utils/directoryservices krb5_conf.py, tests/unit test_krb5.py

NAS-139734 / 25.10.2 / Fix krb5.conf parsing for IPv6 addresses (by anodos325) (#18187)

This commit fixes our IPv6 address insertion into the krb5.conf file.
The bug has been long-standing, but was exposed to broader public in
25.10.1 where we started to auto-detect KDCs and insert them into our
config file via middleware in order to accomodate environments where DNS
is largely broken / unreliable.

Original PR: https://github.com/truenas/middleware/pull/18183

---------

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+182-0tests/unit/test_krb5.py
+21-4src/middlewared/middlewared/utils/directoryservices/krb5_conf.py
+203-42 files

NetBSD/pkgsrc-wip c2e76b7. Makefile, polybar Makefile distinfo

polybar: add new package

Incomplete, uses sys/inotify.h
DeltaFile
+32-0polybar/Makefile
+5-0polybar/distinfo
+4-0polybar/PLIST
+3-0polybar/DESCR
+3-0Makefile
+1-0polybar/TODO
+48-06 files

LLVM/project 79c281acompiler-rt/lib/asan asan_allocator.cpp, compiler-rt/test/asan/TestCases/Windows rtlsizeheap_zero.cpp

[compiler-rt][ASan][Windows] Fix false positive for zero sized rtl allocations
DeltaFile
+107-0compiler-rt/test/asan/TestCases/Windows/rtlsizeheap_zero.cpp
+44-0compiler-rt/lib/asan/asan_allocator.cpp
+151-02 files

FreeNAS/freenas 147603csrc/middlewared/middlewared/utils/directoryservices krb5_conf.py, tests/unit test_krb5.py

NAS-139734 / 26.0.0-BETA.1 / Fix krb5.conf parsing for IPv6 addresses (#18183)

This commit fixes our IPv6 address insertion into the krb5.conf file.
The bug has been long-standing, but was exposed to broader public in
25.10.1 where we started to auto-detect KDCs and insert them into our
config file via middleware in order to accomodate environments where DNS
is largely broken / unreliable.
DeltaFile
+182-0tests/unit/test_krb5.py
+21-4src/middlewared/middlewared/utils/directoryservices/krb5_conf.py
+203-42 files

FreeBSD/src 66797b4usr.sbin/pw pw.8

pw.8: spell
DeltaFile
+1-1usr.sbin/pw/pw.8
+1-11 files

Linux/linux 1e83ccdkernel/sched core.c sched.h

sched/mmcid: Don't assume CID is CPU owned on mode switch

Shinichiro reported a KASAN UAF, which is actually an out of bounds access
in the MMCID management code.

   CPU0                                         CPU1
                                                T1 runs in userspace
   T0: fork(T4) -> Switch to per CPU CID mode
         fixup() set MM_CID_TRANSIT on T1/CPU1
   T4 exit()
   T3 exit()
   T2 exit()
                                                T1 exit() switch to per task mode
                                                 ---> Out of bounds access.

As T1 has not scheduled after T0 set the TRANSIT bit, it exits with the
TRANSIT bit set. sched_mm_cid_remove_user() clears the TRANSIT bit in
the task and drops the CID, but it does not touch the per CPU storage.
That's functionally correct because a CID is only owned by the CPU when

    [18 lines not shown]
DeltaFile
+3-4kernel/sched/core.c
+4-2kernel/sched/sched.h
+7-62 files

LLVM/project 612ddd8llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize BUILD.gn

[gn build] Port 0215f6b6cf81
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/BUILD.gn
+1-01 files

FreeNAS/freenas 74d08dfsrc/middlewared/middlewared/alert/source license_status.py, src/middlewared/middlewared/plugins alert.py support.py

NAS-139600 / 25.10.2 / Update text to replace 'ixsystems' and 'iX' with 'TrueNAS (by mgrimesix) (#18185)

DeltaFile
+30-30src/middlewared/middlewared/alert/source/license_status.py
+4-4src/middlewared/middlewared/plugins/alert.py
+1-1src/middlewared/middlewared/plugins/support.py
+1-1src/middlewared/middlewared/plugins/truenas.py
+1-1src/middlewared/middlewared/plugins/update_/utils.py
+1-1src/middlewared_docs/debian/control
+38-386 files

LLVM/project 08f131dcompiler-rt/lib/asan asan_allocator.cpp, compiler-rt/test/asan/TestCases/Windows rtlsizeheap_zero.cpp

[compiler-rt][ASan][Windows] Fix false positive for zero sized rtl allocations
DeltaFile
+107-0compiler-rt/test/asan/TestCases/Windows/rtlsizeheap_zero.cpp
+44-0compiler-rt/lib/asan/asan_allocator.cpp
+151-02 files

FreeNAS/freenas 725e46bsrc/freenas/usr/local/bin truenas-grub.py, src/middlewared/middlewared/pytest/unit/utils test_write_if_changed.py

NAS-139725 / 25.10.2 / Add protections against partially-written truenas-grub.cfg (by anodos325) (#18179)

This commit ensures that we are always atomically replacing the truenas
grub configuration.

Original PR: https://github.com/truenas/middleware/pull/18173

---------

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+0-210src/middlewared/middlewared/pytest/unit/utils/test_write_if_changed.py
+210-0tests/unit/test_write_if_changed.py
+80-2src/middlewared/middlewared/utils/io.py
+8-1src/freenas/usr/local/bin/truenas-grub.py
+298-2134 files

Linux/linux 939faf7drivers/gpu/drm/amd/amdgpu sdma_v7_1_0_pkt_open.h gfx_v12_1.c, drivers/gpu/drm/amd/include/asic_reg/gc gc_12_1_0_sh_mask.h gc_12_1_0_offset.h

Merge tag 'drm-next-2026-02-11' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "Highlights:
   - amdgpu support for lots of new IP blocks which means newer GPUs
   - xe has a lot of SR-IOV and SVM improvements
   - lots of intel display refactoring across i915/xe
   - msm has more support for gen8 platforms
   - Given up on kgdb/kms integration, it's too hard on modern hw

  core:
   - drop kgdb support
   - replace system workqueue with percpu
   - account for property blobs in memcg
   - MAINTAINERS updates for xe + buddy

  rust:
   - Fix documentation for Registration constructors
   - Use pin_init::zeroed() for fops initialization

    [273 lines not shown]
DeltaFile
+44,638-0drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
+12,418-0drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
+8,262-0drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
+5,673-0drivers/gpu/drm/amd/amdgpu/sdma_v7_1_0_pkt_open.h
+4,066-0drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+3,013-0drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_sh_mask.h
+78,070-01,334 files not shown
+156,794-25,7321,340 files

FreeNAS/freenas b52b799src/middlewared/middlewared/utils/directoryservices krb5_conf.py

Address review
DeltaFile
+1-1src/middlewared/middlewared/utils/directoryservices/krb5_conf.py
+1-11 files

FreeBSD/ports 972ecf2multimedia/uxplay distinfo Makefile

multimedia/uxplay: Update to 1.73.2
DeltaFile
+3-3multimedia/uxplay/distinfo
+1-1multimedia/uxplay/Makefile
+4-42 files

LLVM/project d3afa17llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/X86 cost-model.ll

[LV] Don't scalarize loads that need predication in legacy CM.

The legacy cost model tries to scalarize loads that are used as
pointers. Skip if the load would need predicating when scalarized,
because that would incur very high costs, see useEmulatedMaskMemRefHack.

Fixes https://github.com/llvm/llvm-project/issues/180780.
DeltaFile
+83-0llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+3-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+86-32 files

LLVM/project 0215f6bllvm/include/llvm/Analysis DominanceFrontier.h DominanceFrontierImpl.h, llvm/include/llvm/CodeGen MachineDominanceFrontier.h

[DominanceFrontier] Support post-dominators on graphs with single root (#179336)

I plan to use that to optimize mask creation in VPlan predicator by
`or`ing edge masks from the post-dominance frontier instead of all
predecessors in a subsequent patch. Note that it would require to use
the same unmodified post-dom tree for *all* the basic blocks in a VPlan
that is already limited to a particular loopnest so the algorithmic
complexity concerns behind the "deprecation" notice in the beggining of
`DominanceFrontier.h` (and also discussion in the
https://discourse.llvm.org/t/dominance-frontiers/21755 thread) don't
apply for my use case (at least to the best of my understanding).

The change here is to properly use graph-traits for children traversal
plus inline `ForwardDominanceFrontierBase` into `DominanceFrontierBase` now 
that it's used for post-dom-frontier.

Since the only planned use-case is in the vectorizer, I'm adding a
VPlan-base unittest along with this change.


    [2 lines not shown]
DeltaFile
+94-0llvm/unittests/Transforms/Vectorize/VPPostDomFrontierTest.cpp
+18-26llvm/include/llvm/Analysis/DominanceFrontier.h
+6-6llvm/include/llvm/Analysis/DominanceFrontierImpl.h
+4-5llvm/include/llvm/CodeGen/MachineDominanceFrontier.h
+0-2llvm/lib/CodeGen/MachineDominanceFrontier.cpp
+0-1llvm/lib/Analysis/DominanceFrontier.cpp
+122-401 files not shown
+123-407 files

LLVM/project c6329a3llvm/include/llvm/Transforms/Utils MemoryTaggingSupport.h, llvm/lib/Target/AArch64 AArch64StackTagging.cpp

[NFC] [MemoryTagging] pass AllocaInfo to isStandardLifetime (#180311)

DeltaFile
+7-8llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
+2-4llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
+1-2llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+1-2llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+11-164 files

FreeNAS/freenas 4ac91c9src/freenas/usr/local/bin truenas-grub.py

NAS-139743 / 26.0.0-BETA.1 / Fix typo in truenas-grub (#18186)

This commit fixes a typo in keyword arguments in truenas-grub.py. During
refactoring of in-progress code, a keyword argument had its name changed
unexpectedly resulting in mismatch between call-site and function
signature.
DeltaFile
+1-1src/freenas/usr/local/bin/truenas-grub.py
+1-11 files

FreeBSD/src 2b728d3sys/x86/cpufreq hwpstate_amd.c

hwpstate_amd(4): Move 'struct get_cppc_regs_data' & co. closer to use

No functional change (intended).

Sponsored by:   The FreeBSD Foundation
DeltaFile
+22-22sys/x86/cpufreq/hwpstate_amd.c
+22-221 files

FreeBSD/src c6a0eb7sys/x86/cpufreq hwpstate_amd.c

hwpstate_amd(4): Rename '*set_autonomous_hwp*()' => 'enable_cppc*()'

This is to better reflect that we are really enabling CPPC in these
functions and because we are likely to stop activating CPPC autonomous
mode by default in the near future.

No functional change (intended).

Sponsored by:   The FreeBSD Foundation
DeltaFile
+4-4sys/x86/cpufreq/hwpstate_amd.c
+4-41 files

FreeBSD/src a78e7c2sys/x86/cpufreq hwpstate_amd.c

hwpstate_amd(4): Update copyright

Sponsored by:   The FreeBSD Foundation
DeltaFile
+5-0sys/x86/cpufreq/hwpstate_amd.c
+5-01 files

FreeBSD/src 4285340sys/x86/cpufreq hwpstate_amd.c

hwpstate_amd(4): Style: Align 'machdep.hwpstate_amd_cppc_enable'

Align it like the rest.

No functional change (intended).

Sponsored by:   The FreeBSD Foundation
DeltaFile
+1-1sys/x86/cpufreq/hwpstate_amd.c
+1-11 files