[SLP]Support for zext i1 %x modeling as select %x, 1, 0
Model zext i1 %x to in as select i1 %x, in 1, in 0 in case, if there are
other select instructions, which can be combined into a bundle.
Fixes #178403
Recommit after revert in 993e1f66afcfe9da03bd813e669eada341b11d2f
Reviewers: hiraditya, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/180635
InstCombine: Fix broken insert point for fdiv replacement
SimplifyDemandedFPClass isn't properly adjusting the IRBuilder
insert point, so this could insert at the wrong point if the simplification
happens in one of the recursive calls. There are a few more of these
to fix.
tnftp 20260211 release
Changes since tnftp 20230507:
- Improve transfer performance by simplifying socket buffer and
transfer buffer handling.
- Add -b BUFLEN to adjust size of buffer for HTTP response line parsing.
- Add -h HEADER to support custom HTTP headers.
- Add "connect" as a synonym for "open".
- Fix ASCII mode transfers when progress bar is enabled.
- Fix creation of empty downloaded files.
- Exit non-zero if a HTTP transfer is shorter than expected.
- Fix HTTPS through a proxy.
[MLIR][OpenMP] Fix unused variable warning
7c07cb6542a0c5e4340e09a9a247e3e5123c6567 introduced a variable created
in an if statement that is only used in an assertion. Per the coding
guidelines, mark it [[maybe_unused]].
[AMDGPU] Allow hoising of V_READFIRSTLANE_B32 for uniform operand
readfirstlane can be moved across control flow for uniform inputs.
The MachineInstr::NoConvergent attribute allows hoisting
which is otherwise prohibited for a convergent instruction.
[RISCV] Refactor the MC layer SiFive VCIX classes. (#180433)
My initial goal was to name bits {19-15} as either rs1, vs1, or imm as
appropriate.
The VCIX instructions effectively have 3 properties that are combined:
the type of bits 19-15 (determined by funct3), how many vector registers
are sources (determined by funct6), and whether vd is a written or not
(determined by vm).
I found the VCIXInfo class very hard to read and understand. This patch
breaks it up into simpler steps and moves some properties to flags in
the existing VCIXType classs. A new VCIXRs1Info class is added to
contain the properties for bits 19-15. The VCIXInfo now combines the
properties from these 2 classes and the HaveOutputDst flag to create the
various things needed to build the final instruction. To reduce the
number of template arguments, the VCIXInfo is passed all the way down to
the base class.
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[RISCV] Add (BSETI x0, 11) to isLoadImm for optimizeCondBranch (#180820)
optimizeCondBranch is looking for immediates that are 1 apart to rewrite
the branch by sharing a constant. BSETI x0, 11 can be used to produce
2048 which is one more than the largest positive constant produced by
addi.
[MLIR][Python] Remove partial LLVM APIs in python bindings (5/n) (#180644)
This PR continues work from
https://github.com/llvm/llvm-project/pull/178290
Added local helper functions to avoid dependency on LLVM APIs.
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Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
