NetBSD/pkgsrc-wip 00a5e63rust-beta cargo.mk, rust196 cargo.mk

rust196 & beta: follow pkgsrc main
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+3-9rust196/cargo.mk
+3-9rust-beta/cargo.mk
+6-182 files

NetBSD/pkgsrc-wip bd147b2rust195 Makefile distinfo, rust195/files gcc-wrap

remove rust-1.95
DeltaFile
+0-822rust195/Makefile
+0-215rust195/files/gcc-wrap
+0-211rust195/distinfo
+0-146rust195/cargo.mk
+0-128rust195/patches/patch-vendor_memchr-2.7.4_src_memchr.rs
+0-117rust195/options.mk
+0-1,63986 files not shown
+2-4,48692 files

LLVM/project 3a1420eclang/cmake/caches hexagon-unknown-linux-musl-clang-dist.cmake hexagon-unknown-linux-musl-clang-cross-dist.cmake

[Hexagon] Add cmake caches for cross-toolchain distribution build (#201207)

Adds and extends the
clang/cmake/caches/hexagon-unknown-linux-musl-clang* files to drive a
full install-distribution build: host tools, per-target builtins (Linux
and baremetal), and runtimes for hexagon-unknown-linux-musl.
DeltaFile
+180-0clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
+32-0clang/cmake/caches/hexagon-unknown-linux-musl-clang-cross-dist.cmake
+15-0clang/cmake/caches/hexagon-unknown-linux-musl-clang-defaults-dist.cmake
+11-0clang/cmake/caches/generic-allow-shared-imports.cmake
+10-0clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
+248-05 files

LLVM/project 7efcfccllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange atomic-memory-ordering.ll invoke.ll

[LoopInterchange] Identify unsafe instructions for interchange
DeltaFile
+14-36llvm/test/Transforms/LoopInterchange/atomic-memory-ordering.ll
+21-18llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+5-15llvm/test/Transforms/LoopInterchange/invoke.ll
+40-693 files

FreeBSD/ports 25b0ad2net-im/nextcloud-talk distinfo Makefile

net-im/nextcloud-talk: Update to 23.0.6
DeltaFile
+3-3net-im/nextcloud-talk/distinfo
+1-1net-im/nextcloud-talk/Makefile
+4-42 files

FreeBSD/ports 699ecc2mail/nextcloud-mail distinfo Makefile

mail/nextcloud-mail: Update to 5.9.0
DeltaFile
+3-3mail/nextcloud-mail/distinfo
+1-1mail/nextcloud-mail/Makefile
+4-42 files

FreeBSD/ports ee4db0cwww/nextcloud distinfo Makefile

www/nextcloud: Update to 33.0.5
DeltaFile
+3-3www/nextcloud/distinfo
+1-1www/nextcloud/Makefile
+4-42 files

LLVM/project 14299e1llvm/lib/Target/AArch64 AArch64RegisterInfo.td SMEInstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7

The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.
DeltaFile
+15-0llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+5-0llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
+4-0llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+1-1llvm/lib/Target/AArch64/SMEInstrFormats.td
+25-14 files

LLVM/project d3b5f2ellvm/lib/Target/AArch64 AArch64RegisterInfo.td SMEInstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Address more CR comments
DeltaFile
+6-8llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+10-1llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+2-2llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+1-1llvm/lib/Target/AArch64/SMEInstrFormats.td
+19-124 files

LLVM/project 932aff7llvm/lib/Target/AArch64 AArch64RegisterInfo.td

fixup! Address CR comments
DeltaFile
+10-19llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+10-191 files

LLVM/project 3d38084llvm/lib/Target/AMDGPU GCNSubtarget.cpp

Fix typo

Change-Id: I0811d29cdaddc35f2a17415dbf2a8f25e634f1d0
DeltaFile
+1-1llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+1-11 files

FreeNAS/freenas 683b7e0

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

LLVM/project ee10231libc/include stdio.yaml, libc/include/llvm-libc-macros _LIBC_MODULAR_FORMAT_PRINTF.h _LIBC_MODULAR_FORMAT_PRINTF-disable.h

[libc] Add explicit format attributes for modular printf (#201212)

We had been relying on compiler-generated format attributes when using
the modular_format attribute for printf-family functions, but this is
not applied in -ffreestanding mode. When modular format is enabled, libc
is explicitly asserting the semantics of these functions, so it should
be explicit about the format attributes as well to keep them from
breaking in -ffreestanding.

Generated by Gemini, reviewed and edited by hand.
DeltaFile
+8-8libc/include/stdio.yaml
+4-2libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF.h
+1-1libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF-disable.h
+13-113 files

FreeNAS/freenas 807a387src/middlewared/middlewared/api/v26_0_0 system_product.py, src/middlewared/middlewared/api/v27_0_0 system_product.py

NAS-141068 / 27.0.0-BETA.1 / Properly handle VM feature flag (#19027)

## Context

Middleware should expose the VM entitlement as "VMS" at the API boundary
and to any consumer that inspects license features. The signed license
PEM and signing daemon continue to carry "VM" as the JSON key, and
existing customer PEMs can't be re-keyed without re-signing, so the
translation has to happen middleware-side.

## Solution

A single `FEATURE_NAME_MAP` in license_utils.py translates "VM" → "VMS"
for both the daemon-signed and legacy parsers (the legacy-only JAILS →
APPS entry sits in the same map; it's a no-op on the modern path since
the daemon never emits "JAILS"). v26 and v27 SystemFeatureEnabledArgs
both accept "VMS" and carry from_previous / to_previous adapters so v25
/ v26 clients passing "VM" are translated transparently.
DeltaFile
+77-0src/middlewared/middlewared/pytest/unit/plugins/truenas/test_license_utils.py
+7-1src/middlewared/middlewared/api/v26_0_0/system_product.py
+7-1src/middlewared/middlewared/api/v27_0_0/system_product.py
+2-3src/middlewared/middlewared/plugins/truenas/license_legacy_utils.py
+2-2src/middlewared/middlewared/plugins/truenas/license_utils.py
+1-1src/middlewared/middlewared/pytest/unit/plugins/truenas/test_license_legacy_utils.py
+96-81 files not shown
+97-97 files

LLVM/project cf9bf34llvm/lib/Target/AMDGPU AMDGPUPreloadKernArgProlog.cpp, llvm/test/CodeGen/AMDGPU lds-dma-workgroup-release.ll preload-kernarg-header.ll

[AMDGPU] Fix backward compatibility kernarg preload prolog base offset (#201355)

Backward compatibility preload prolog loaded args from kernarg-segment
byte 0, but on non-AMDHSA triples the explicit args start at
`getExplicitKernelArgOffset()` (value: 36), so preloaded SGPRs held the
runtime header instead of the arguments
DeltaFile
+146-168llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
+32-6llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
+179-1753 files

LLVM/project cd75a7dllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 clmul-vector.ll clmul.ll

[SelectionDAG] Fix missed optimization for CLMUL where one operand is all ones (#200592)

Fixes #200556

This special case is equivalent to a "parallel prefix XOR" or "bitwise
parity" operation, which can be expanded to a logarithmic amount of
bitwise operations instead of a linear amount (relative to the bit
width). When other bitwise operations such as BDEP and BEXT are
expanded, they rely on that operation being lowered to a CLMUL directly
or expanded to this efficient form.

See also
- #200570 (this PR needs this fix to have good codegen)
DeltaFile
+1,003-8,015llvm/test/CodeGen/X86/clmul-vector.ll
+859-0llvm/test/CodeGen/X86/clmul.ll
+12-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+1,874-8,0153 files

FreeBSD/ports 374f76edatabases/py-oxyde-core distinfo Makefile.crates

databases/py-oxyde-core: Update 0.5.0 => 0.6.2

Changelogs:
- https://github.com/mr-fatalyst/oxyde/releases/tag/core-v0.6.0
- https://github.com/mr-fatalyst/oxyde/releases/tag/core-v0.6.1
- https://github.com/mr-fatalyst/oxyde/releases/tag/core-v0.6.2
Commit log:
https://github.com/mr-fatalyst/oxyde/compare/core-v0.5.0...core-v0.6.2

PR:             295801
Reported by:    Goran Mekić <meka at tilda.center> (maintainer)
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+151-97databases/py-oxyde-core/distinfo
+74-47databases/py-oxyde-core/Makefile.crates
+6-7databases/py-oxyde-core/Makefile
+231-1513 files

LLVM/project 15375d8clang/include/clang/Options FlangOptions.td, flang/docs OpenACC-extensions.md

[flang][openacc] change option feature flag names to address comments. (#200037)

- Fixes FeatureFlags and CLI flags to use OpenACC instead of ACC.
- Offline comments further refined the name to be
OpenACCDefaultNoneScalarsStrict
- Which changes the semantics requiring the user to opt out of the
default behavior, instead of opt-in to an extension.
- Also makes the CLI flag OptOut instead of OptIn to match the cli
behavior.
- Gets rid of the unneeded warning flag since FeatureFlags have both a
disabled bit and a warning bit.
- Updates old test for these changes and adds a new test to document all
the different cli configurations.
DeltaFile
+45-0flang/test/Semantics/OpenACC/acc-default-none-scalars-strict.f90
+14-8flang/docs/OpenACC-extensions.md
+11-11flang/test/Semantics/OpenACC/acc-default-none-scalars.f90
+8-5flang/lib/Semantics/resolve-directives.cpp
+5-5flang/lib/Frontend/CompilerInvocation.cpp
+3-2clang/include/clang/Options/FlangOptions.td
+86-313 files not shown
+90-379 files

LLVM/project 06ac45dllvm/lib/CodeGen/GlobalISel CallLowering.cpp, llvm/test/CodeGen/X86/GlobalISel calllowering-inalloca.ll

[GISel][CallLowering] Set byval flag for inalloca/preallocated args (#200600)

GlobalISel asserts when lowering a function with an `inalloca` or
`preallocated` argument:

> TargetCallingConv.h:183: void
llvm::ISD::ArgFlagsTy::setByValSize(unsigned): Assertion `isByVal() &&
!isByRef()' failed.

https://godbolt.org/z/jWr4enjaj

`addFlagsFromAttrSet()` sets the `InAlloca`/`Preallocated` flags but
never `ByVal`.
`setArgFlags()` then calls `Flags.setByValSize()` for any non-`ByRef`
indirect argument which asserts `isByVal()`.

`SelectionDAGISel::LowerArguments()` avoids this by deliberately also
setting the `ByVal` flag for `inalloca`/`preallocated`, this change
makes the GlobalISel side match that behavior.
DeltaFile
+23-0llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
+17-3llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+40-32 files

FreeBSD/ports 8ae0cc9misc/py-comfy-aimdo distinfo Makefile

misc/py-comfy-aimdo: update 0.4.7 → 0.4.8
DeltaFile
+3-3misc/py-comfy-aimdo/distinfo
+1-1misc/py-comfy-aimdo/Makefile
+4-42 files

FreeBSD/ports fa0fba0misc/lean-ctx distinfo Makefile

misc/lean-ctx: update 3.7.0 → 3.7.1
DeltaFile
+79-3misc/lean-ctx/distinfo
+40-2misc/lean-ctx/Makefile
+119-52 files

FreeBSD/ports 5357337net/sing-box distinfo Makefile

net/sing-box: update 1.13.12 → 1.13.13
DeltaFile
+5-5net/sing-box/distinfo
+1-1net/sing-box/Makefile
+6-62 files

FreeBSD/ports 0e6be55misc/py-langchain distinfo Makefile

misc/py-langchain: update 1.3.2 → 1.3.4
DeltaFile
+3-3misc/py-langchain/distinfo
+2-2misc/py-langchain/Makefile
+5-52 files

FreeBSD/ports 082c055misc/py-langgraph distinfo Makefile

misc/py-langgraph: update 1.2.3 → 1.2.4
DeltaFile
+3-3misc/py-langgraph/distinfo
+1-1misc/py-langgraph/Makefile
+4-42 files

FreeBSD/ports aac0b8dmisc/py-langsmith Makefile distinfo

misc/py-langsmith: update 0.7.34 → 0.8.8
DeltaFile
+6-1misc/py-langsmith/Makefile
+3-3misc/py-langsmith/distinfo
+9-42 files

FreeBSD/ports 2c8cb6cmultimedia/py-pretty_midi Makefile distinfo

multimedia/py-pretty_midi: update 0.2.10 → 0.2.11
DeltaFile
+7-4multimedia/py-pretty_midi/Makefile
+3-3multimedia/py-pretty_midi/distinfo
+10-72 files

FreeBSD/ports bf4406fmisc/ollama Makefile distinfo, misc/ollama/files freebsd-compatibility.patch patch-discover_cpu__freebsd.go

misc/ollama: update 0.24.0 → 0.30.0
DeltaFile
+3-162misc/ollama/files/freebsd-compatibility.patch
+113-31misc/ollama/Makefile
+69-0misc/ollama/files/patch-discover_cpu__freebsd.go
+17-33misc/ollama/files/patch-x_imagegen_mlx_mlx.go
+0-40misc/ollama/files/patch-x_imagegen_mlx_CMakeLists.txt
+13-11misc/ollama/distinfo
+215-2773 files not shown
+229-3069 files

FreeBSD/ports 4ce9254misc/antigravity-cli distinfo Makefile

misc/antigravity-cli: update 1.0.3 → 1.0.4
DeltaFile
+5-5misc/antigravity-cli/distinfo
+2-2misc/antigravity-cli/Makefile
+7-72 files

FreeBSD/ports 8ab753cmisc/fabric distinfo Makefile

misc/fabric: update 1.4.453 → 1.4.454
DeltaFile
+5-5misc/fabric/distinfo
+1-1misc/fabric/Makefile
+6-62 files

LLVM/project 5c96694cross-project-tests/debuginfo-tests/dexter/dex/evaluation StateMatch.py

Remove unused class
DeltaFile
+0-6cross-project-tests/debuginfo-tests/dexter/dex/evaluation/StateMatch.py
+0-61 files