LLVM/project 3c60be2utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Fix build for 8e85a42d5b (#182359)

DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project dcd2b08llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rv64p.ll

[RISCV] Use FSHR in LowerShiftRightParts for P extension on RV64. (#181234)

We can't do the NSRLI trick on RV64, but we can use srx similar to what
we do in LowerShiftLeftParts. We need an additional fixup step for the
FSHR result that NSRLI doesn't need.

Assisted-by: claude
DeltaFile
+40-14llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+11-29llvm/test/CodeGen/RISCV/rv64p.ll
+51-432 files

LLVM/project 3c6523dflang/lib/Optimizer/Transforms FIRToMemRef.cpp, flang/test/Transforms/FIRToMemRef array-coor-block-arg.mlir no-declare.mlir

Revert "[flang] Lowering a ArrayCoorOp to arithmetic computations whe… (#182365)

This reverts commit 2bd23d3fa688d0e25c8492ceeaa251af4759d559.
DeltaFile
+15-14flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
+0-28flang/test/Transforms/FIRToMemRef/array-coor-block-arg.mlir
+6-7flang/test/Transforms/FIRToMemRef/no-declare.mlir
+21-493 files

LLVM/project b26c617mlir/lib/Target/LLVM/ROCDL Target.cpp

Change AMDGPU target initialization condition
DeltaFile
+1-1mlir/lib/Target/LLVM/ROCDL/Target.cpp
+1-11 files

LLVM/project ae66e34llvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/lib/CodeGen MachineVerifier.cpp PeepholeOptimizer.cpp

[NFC][CodeGen] Add helper function to check SubReg validity (#181489)

Add function `isSubRegValidForRegClass` to check if a sub-register index
can be used with a register class and use it in MIR verifier and a few
other places.
DeltaFile
+7-17llvm/lib/CodeGen/MachineVerifier.cpp
+14-5llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+2-6llvm/lib/CodeGen/PeepholeOptimizer.cpp
+1-1llvm/lib/CodeGen/TargetRegisterInfo.cpp
+1-1llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
+25-305 files

LLVM/project aeaea7allvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine bitcast-select-const-vector.ll copysign.ll

InstCombine: Fold bitcast of vector with constant to scalar (#179042)

Fold bitcast (select cond, val, const) ->
  select cond, (bitcast val), (bitcast const)

Rocm device libs has an unfortunate amount of code that does bithacking
on the sign bit of double values by casting to <2 x i32> and operating
on the high element. This breaks value tracking optimizations on the
fp value.

The existing transform would only do this if the input to the select was
also a bitcast with a single use, and if it didn't convert between
vector and scalar.
DeltaFile
+129-0llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll
+20-5llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+3-4llvm/test/Transforms/InstCombine/copysign.ll
+3-3llvm/test/Transforms/InstCombine/fold-bin-operand.ll
+155-124 files

OPNSense/core 9a691f5src/etc/inc/plugins.inc.d radvd.inc

radvd: fold $primary identification into $stanzas for #9815
DeltaFile
+9-8src/etc/inc/plugins.inc.d/radvd.inc
+9-81 files

LLVM/project 918ef6cllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-assert-align.mir assert-align.ll

[AMDGPU][GISel] Add RegbankLegalize Rules for G_ASSERT_ALIGN (#182353)

DeltaFile
+217-9llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
+10-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
+228-103 files

LLVM/project 17aa4bbclang/lib/StaticAnalyzer/Checkers/WebKit PtrTypesSemantics.cpp, clang/test/Analysis/Checkers/WebKit uncounted-local-vars.cpp

[alpha.webkit.UncountedLocalVarsChecker] Handle null Type in CanTriviallyDestruct (#182129)

Added an early exit for when CanTriviallyDestruct encounters a QualType
without a Type.
DeltaFile
+26-0clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
+3-2clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
+29-22 files

LLVM/project ec8b9caclang/lib/CodeGen CGDebugInfo.cpp, clang/test/DebugInfo/CXX callsite-edges.cpp callsite-derived.cpp

Revert "[clang][DebugInfo] Add virtuality call-site target informatio… (#182343)

…n in DWARF. (#167666)"

This reverts commit 418ba6e8ae2cde7924388142b8ab90c636d2c21f.

The commit caused an ICE due to hitting unreachable in
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp:1307

Fixes #182337
DeltaFile
+0-93clang/test/DebugInfo/CXX/callsite-edges.cpp
+0-72cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/callsite-dwarf.cpp
+0-58clang/test/DebugInfo/CXX/callsite-derived.cpp
+0-48clang/test/DebugInfo/CXX/callsite-base.cpp
+1-28llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+0-17clang/lib/CodeGen/CGDebugInfo.cpp
+1-31618 files not shown
+23-38124 files

LLVM/project 0dafeb9llvm/include/llvm/Target/GlobalISel Combine.td, llvm/test/CodeGen/AArch64/GlobalISel combine-add.mir combine-addv.mir

[GIsel] import `(not (add X, -1)) -> (neg X)` to GlobalISel (#181640)

We port the rewrite `(not (add X, -1)) -> (neg X)` from SelectionDAG to
GlobalISel. I contemplated adding a `G_NEG` primitive initially, but
given that the [SelectionDAG pattern rewrites to a
subtraction](https://github.com/llvm/llvm-project/blob/20aff2085c358d3e112b245494161ddb9ffe0410/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L1649),
I implemented the rhs of the rewrite as a subtraction directly,
specifying the comment accordingly.
DeltaFile
+51-0llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
+26-0llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
+9-0llvm/include/llvm/Target/GlobalISel/Combine.td
+86-03 files

LLVM/project 413cafallvm/lib/Transforms/Scalar LoopUnrollPass.cpp, llvm/test/Transforms/LoopUnroll debug.ll

[LoopUnrollPass] Remove redundant debug message in `tryToUnrollLoop()` (#181954)

Remove the redundant debug message. 

While we're here, adopt the same debug message language that's used in
#178476 and use an `if` instead of a single `case` `switch` statement.
DeltaFile
+7-10llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+2-4llvm/test/Transforms/LoopUnroll/debug.ll
+9-142 files

LLVM/project ea27498llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU sched_mfma_rewrite_diff_types.mir

[AMDGPU] Fix handling of setting register classes in MFMA scheduler rewrite stage (#181047)

Fixes problem with setting/resetting register classes in the MFMA
rewrite sched stage. The code assumed that the dest and OpC would be the
same class. This is not true if one uses subregs. This fixes issue
#177696.
DeltaFile
+173-0llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
+23-11llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+196-112 files

FreeNAS/freenas ed9b6dctests/api2 test_api.py

Enhance test_versions to also handle new version format
DeltaFile
+14-2tests/api2/test_api.py
+14-21 files

pfSense/pfsense ccaf33esrc/etc/inc gwlb.inc

Relax type requirements for gateway status helper functions

Some callers of the helper functions do not validate the arguments.
Handle this in the helper functions for better compatibility.

Followup to ddd366b3706a7c24d2406b9ccfdca76a0dca4be4.
DeltaFile
+22-11src/etc/inc/gwlb.inc
+22-111 files

LLVM/project efb397clibc/src/__support/mathvec expf.h common_constants.h, libc/src/mathvec CMakeLists.txt

[libc][mathvec] Initial commit for LIBC vector math component (#173058)

Created mathvec directories and unittest framework for vector math
functions, as well as an initial implementation of vector expf, which is
presently CR for round-to-nearest.

---------

Co-authored-by: Pierre Blanchard <pierre.blanchard at arm.com>
DeltaFile
+131-0libc/test/src/mathvec/expf_test.cpp
+84-0libc/src/__support/mathvec/expf.h
+61-0libc/test/UnitTest/SIMDMatcher.h
+43-0libc/src/mathvec/CMakeLists.txt
+40-0libc/src/__support/mathvec/common_constants.h
+34-0libc/src/__support/mathvec/expf_utils.h
+393-014 files not shown
+519-420 files

FreeNAS/freenas 487333csrc/middlewared/middlewared/api/v26_0_0 interface.py, src/middlewared/middlewared/plugins network.py

touch up
DeltaFile
+13-9src/middlewared/middlewared/plugins/network.py
+2-1src/middlewared/middlewared/api/v26_0_0/interface.py
+15-102 files

LLVM/project eec7a2flldb/source/Target RegisterContext.cpp

[lldb] Remove redundant nullptr check (NFC) (#182352)

`target` cannot be null because `target_sp` is non-null.
DeltaFile
+2-6lldb/source/Target/RegisterContext.cpp
+2-61 files

LLVM/project 2979654clang/lib/CIR/CodeGen CIRGenCUDANV.cpp, clang/test/CIR/CodeGenCUDA kernel-call.cu

[CIR][HIP] Add Stub body emission test coverage and Fix kernelHandle storage (#179823)

Related: https://github.com/llvm/llvm-project/issues/179278,
https://github.com/llvm/llvm-project/issues/175871

Besides adding extra test coverage for hip:

Given that HIP represents kernel handles as a global Op. In my previous
patch there was a slight miss-use of the CIR api. since
`getOrCreateCIRGlobal` expects a VarDecl for location info but
`gd.getDecl()` (in this scope) is a FunctionDecl, trying to cast it to
the proper type would provoke that value to be null. Causing a crash
when generating the proper mlir location from the AST. here:
https://github.com/llvm/llvm-project/blob/fab5b1858d02ffed88b76d33f7c691ee4e0c82fb/clang/lib/CIR/CodeGen/CIRGenModule.cpp#L731

Fixed it by using `createGlobalOp` which allows to use the location from
the proper funcOp itself.
DeltaFile
+12-3clang/test/CIR/CodeGenCUDA/kernel-call.cu
+5-8clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+17-112 files

FreeBSD/ports ef3d992mail/mu Makefile distinfo

mail/mu: Update 1.12.13 => 1.12.15

Changelog:
https://github.com/djcb/mu/releases/tag/v1.12.14
https://github.com/djcb/mu/releases/tag/v1.12.15

Improve port:
- Fix build with emacs installed.
- Fix warning from portclippy.

PR:     293277 292576
MFH:    2026Q1
(cherry picked from commit 863e7d211cb9ec53bda42218f2bd9f9b704efa33)
DeltaFile
+3-6mail/mu/Makefile
+3-5mail/mu/distinfo
+2-0mail/mu/pkg-plist
+8-113 files

LLVM/project a7b5cb8mlir/lib/Dialect/Tosa/IR TosaOps.cpp, mlir/test/Dialect/Tosa verifier.mlir tosa-infer-shapes.mlir

[mlir][tosa] Improve slice op verifier (#181889)

The slice op verifier was missing checks on the values of start and size
inputs. Similar to other op verifiers, shape_t const inputs have been
checked for validity against the spec. The commit adds checks for the
following conditions:
- start values must be non-negative
- size values must be > 0
- start + size must be less than or equal to the input dimension size
- the output shape must be consistent with the size values

The commit also allows kInferableDimSize values (-1) to be passed in for
start and size, which are used to indicate that the dimension size can
be inferred by the compiler. The verifier will skip checks for any start
or size value that is kInferableDimSize. With shape expressions being
added, we should no longer require these values, but removal will be
handled in a separate commit.
DeltaFile
+60-6mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+50-0mlir/test/Dialect/Tosa/verifier.mlir
+0-36mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+12-12mlir/test/Dialect/Tosa/ops.mlir
+9-8mlir/test/Dialect/Tosa/canonicalize.mlir
+7-7mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
+138-698 files not shown
+159-9014 files

LLVM/project 30eb036llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'main' into users/amara/outliner-bundles
DeltaFile
+121,421-138,357llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,316-44,830llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,890-0polly/lib/External/isl/include/isl/cpp.h
+317,254-201,73412,854 files not shown
+1,481,037-829,89512,860 files

LLVM/project 1a6b44bmlir/lib/Dialect/ArmSME/Transforms TileAllocation.cpp, mlir/test/Dialect/ArmSME tile-allocation-nested-regions.mlir

[mlir][ArmSME] Replace nested-region assertion in tile allocation with diagnostic (#181934)

Replace the nested-region assertion in ArmSME tile allocation with a
proper diagnostic and graceful failure.

Fixes #181593
DeltaFile
+25-0mlir/test/Dialect/ArmSME/tile-allocation-nested-regions.mlir
+17-8mlir/lib/Dialect/ArmSME/Transforms/TileAllocation.cpp
+42-82 files

OpenBSD/ports HZJH1Qsdevel/libuv Makefile distinfo

   devel/libuv: Update to 1.52.0

   ok sthen@
VersionDeltaFile
1.33+2-3devel/libuv/Makefile
1.13+2-2devel/libuv/distinfo
+4-52 files

OpenBSD/ports 5VOXfcRdevel/esbuild distinfo Makefile

   devel/esbuild: Update to 0.27.3

   from Igor Zornik (Maintainer), thanks
VersionDeltaFile
1.17+2-2devel/esbuild/distinfo
1.18+1-1devel/esbuild/Makefile
+3-32 files

LLVM/project a8f2e80mlir/test/mlir-tblgen gen-op-doc.td openmp-ops.td, mlir/tools/mlir-tblgen OpDocGen.cpp

[MLIR][tblgen] Honor `-dialect` in `-gen-{attrdef,op,typedef,enum}-doc` (#182183)

Make all dialect documentation generators use the same set of records as
`-gen-dialect-doc`, which honors the `-dialect` tblgen option to filter
records by dialect. Add a `-keep-op-source-order` option to allow
`-gen-op-doc` to continue producing unsorted op lists if needed.

This commit factors the record collection, filtering, and sorting
performed in `emitDialectDoc` out into a separate `collectRecords`
function, returning a `DialectRecords` with the results. The emit
functions now all accept a `DialectRecords` argument instead of
collecting records themselves. Most changes are mechanical renamings and
moving code around.

This fixes a confusing issue where `gen-dialect-doc` would produce the
entire documentation for a dialect, but individual calls to
`gen-attrdef-doc` and the like would seemingly operate on a different
set of records, potentially covering multiple dialects. This all produce
the overall documentation now.
DeltaFile
+148-114mlir/tools/mlir-tblgen/OpDocGen.cpp
+20-0mlir/test/mlir-tblgen/gen-op-doc.td
+1-1mlir/test/mlir-tblgen/openmp-ops.td
+169-1153 files

FreeBSD/ports 863e7d2mail/mu Makefile distinfo

mail/mu: Update 1.12.13 => 1.12.15

Changelog:
https://github.com/djcb/mu/releases/tag/v1.12.14
https://github.com/djcb/mu/releases/tag/v1.12.15

Improve port:
- Fix build with emacs installed.
- Fix warning from portclippy.

PR:     293277 292576
MFH:    2026Q1
DeltaFile
+3-6mail/mu/Makefile
+3-5mail/mu/distinfo
+2-0mail/mu/pkg-plist
+8-113 files

FreeNAS/freenas d168883src/middlewared/middlewared/api/v26_0_0 interface.py, src/middlewared/middlewared/plugins network.py

draft
DeltaFile
+22-2src/middlewared/middlewared/plugins/network.py
+12-1src/middlewared/middlewared/api/v26_0_0/interface.py
+34-32 files

FreeBSD/src 818971cusr.sbin/bhyve rfb.c

bhyve: Fix unchecked stream I/O in RFB handler

Convert rfb_send_* helpers to return status codes and check their
results. Add missing checks for stream_read() and stream_write() returns
during the handshake in rfb_handle() to avoid acting on failed I/O.

Signed-off-by:  Hayzam Sherif <hayzam at gmail.com>

Reviewed by:    markj
MFC after:      2 weeks
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D55343
DeltaFile
+54-22usr.sbin/bhyve/rfb.c
+54-221 files

FreeBSD/src 0213827share/misc usb_vendors

usb_vendors: update to 2025.12.13

(cherry picked from commit 8d4c1043bb0630710cbea9f744cdaef499c0ed79)
(cherry picked from commit 2f866e0547bd85e4fc66cf5468e8349931e365be)
DeltaFile
+3-2share/misc/usb_vendors
+3-21 files