[CIR] Regenerate CHECK lines for two callconv opt-out tests (#225189)
Neither `union.c` nor `paren-list-agg-init.cpp` is blocked by the
calling convention lowering pass any more, and both compile clean with
it running. Remove the `-fno-clangir-call-conv-lowering` opt-out and
update their CHECK lines. The coerced parameters and returns they now
pin match classic.
The bodies still differ, since CIR round-trips the record through a
fresh coerce slot, so those fragments move to the `LLVMCIR` and `OGCG`
prefixes the file already declares. Four `define` lines in
`paren-list-agg-init.cpp` wildcarded their return type and now pin it.
Assisted-by: Cursor / claude-opus-5
filesystems/ntfs2btrfs: update the port to version 20260810
- Due to use of C++ modules now demands LLVM 17+ from ports
- Drop dependency on `devel/libfmt' in favor of std::format
Reported by: portscout
[AMDGPU][MC] Upstream gfx11/gfx12 true16 assembler test coverage (#223826)
Upstream new assembler test cases, covering true16 .l/.h operands and
op_sel
handling that had no upstream coverage.
[AMDGPU] Remove two VOPD instructions from gfx1250 and gfx13.
V_DUAL_DOT2ACC_F32_F16 and V_DUAL_DOT2ACC_F32_BF16 were removed from both
gfx1250 and gfx13.
Fixes LCOMPILER-2684.
[SLP] Reland: More accurately cost RISCV scalar splats (#224766)
Originally #213104, reverted due to assertion failure in cases of
reordered gather nodes.
Backends may have a fast path for splatting scalar operands (i.e. rather
than generating the splat vector, the vector instruction may be able to
take a scalar operand), for example RISCV `vfoo.vx` instructions. Pass a
hint to the TTI when costing the insert/shuffle sequence in such cases.
Fixes #212413.
Assisted By: Codex
[DebugInfo] Fix overflow in DWARFDebugLine::SectionParser (#224770)
Adding a DWARF64 unit length can overflow and wrap back into the
section, causing an infinite loop. Saturate the addition so an
overflowing offset fails the bounds check.
rdar://186810393
[NVPTX] Preserve volatile on atomic local loads and stores (#224719)
Local loads and stores discard atomic ordering during instruction
selection, but volatile accesses with acquire, release, or seq_cst
ordering also lose the volatile qualifier. Preserve volatile for all
valid load/store orderings when local volatile instructions are
supported. Follow up to #217764.
[WebKit Checkers] Trace through temporaries in tryToFindPtrOrigin (#224877)
RefPtr checking skips temporaries, reporting a path through any
temporary as unsafe. This is mostly correct, but not always. For
example, the following is a false positive:
// makeKey() returns a temporary
RefCountable* p = condition(makeKey()) ? guardian.ptr() : nullptr;
In the upcoming Borrow checker, it's even more important to trace
through temporaries because not tracing an expression can drop a
`lifetimebound` link, resulting in false **negatives**.
This patch adds tracing through temporaries. The logic is:
* In function call arguments, temporaries are lifetime safe because the
full expression does not end until the call returns
* In ranged for loops, temporaries are lifetime safe because lifetime
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[clang][FreeBSD] Enable KASAN and KMSAN for riscv64 (#202288)
enables KASAN and KMSAN for the riscv64 freebsd target in the Clang
driver.
The corresponding FreeBSD kernel runtime support for riscv64 KASAN is
currently under active review.
Depends on: https://reviews.freebsd.org/D57381
Co-authored-by: aokblast <aokblast at FreeBSD.org>
Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)
This relands #217055
The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.
[AMDGPU] Update based on review feedback
Replace the lambda with the check inlined at both sites, and report a fatal
error when neither a free SGPR nor FrameReg is available, rather than
silently falling back to the spilling scavenge.
[AMDGPU] Use the scavenger to test whether SCC is live after MI
The register scavenger is stepped backwards to the liveness state
immediately after MI, so RS->isRegUsed(SCC) already answers "is SCC live
after MI" directly. Replace the hand-rolled test with that query.
[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering
When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge
that register with AllowSpill=false.
