LLVM/project 8d34545llvm/lib/IR Verifier.cpp, llvm/test/Verifier dbg-type-line-without-file.ll

Introduce and use Verifier::visitDIType (#189067)

This adds a new method Verifier::visitDIType, and then changes method
for subclasses of DIType to call it. The new method just dispatches to
DIScope and adds a file/line check inspired by
Verifier::visitDISubprogram.
DeltaFile
+19-6llvm/lib/IR/Verifier.cpp
+13-0llvm/test/Verifier/dbg-type-line-without-file.ll
+2-2mlir/test/Target/LLVMIR/Import/debug-info.ll
+34-83 files

LLVM/project f33e9fallvm/include/llvm/Transforms/IPO SampleProfileMatcher.h, llvm/lib/Transforms/IPO SampleProfileMatcher.cpp

[SampleProfile] Fix FuncMappings key mismatch for renamed functions in stale profile matching (#187899)

Fix a bug where `distributeIRToProfileLocationMap` fails to find
location mappings from IR to profile for renamed functions because
`FuncMappings` is indexed by the IR function name while
`distributeIRToProfileLocationMap` looks up by the profile function
name. Fixed by making `FuncMappings` to use profile function name as
key.
DeltaFile
+56-0llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-renaming-lineshift.prof
+24-0llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-renaming.ll
+2-2llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
+1-1llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+83-34 files

LLVM/project 85fb6balldb/include/lldb/Utility Stream.h, lldb/source/Commands CommandObjectTarget.cpp CommandObjectMemory.cpp

[lldb][Utility] Remove address size from Stream class (NFC) (#190375)

It violates abstraction. Luckily, it was used only in two places, see
DumpDataExtractor.cpp and CommandObjectMemory.cpp.
DeltaFile
+0-30lldb/source/Commands/CommandObjectTarget.cpp
+4-21lldb/include/lldb/Utility/Stream.h
+2-10lldb/source/Utility/Stream.cpp
+4-5lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+3-4lldb/source/Utility/StreamString.cpp
+2-5lldb/source/Commands/CommandObjectMemory.cpp
+15-7518 files not shown
+41-10824 files

FreeNAS/freenas 30dc36esrc/middlewared/middlewared/plugins/pool_ sed.py

growing weary
DeltaFile
+5-1src/middlewared/middlewared/plugins/pool_/sed.py
+5-11 files

FreeBSD/ports 6b9beb8devel/sdl3 Makefile

devel/sdl3: enable UDEV for KMSDRM and by default

As reported in 294156, UDEV must be enabled along with KMSDRM.
Enable it by default as well in consistence with upstream setting.

PR:             294156
Reported by:    quentin.thebault at defenso.fr
DeltaFile
+3-2devel/sdl3/Makefile
+3-21 files

FreeBSD/ports d21a34fdevel/sdl3 Makefile distinfo, devel/sdl3/files patch-src_hidapi_SDL__hidapi.c patch-cmake_FindLibUSB.cmake

devel/sdl3: update 3.2.30 → 3.4.2

PR:             294157
DeltaFile
+0-20devel/sdl3/files/patch-src_hidapi_SDL__hidapi.c
+14-6devel/sdl3/Makefile
+0-11devel/sdl3/files/patch-cmake_FindLibUSB.cmake
+3-3devel/sdl3/distinfo
+1-0devel/sdl3/pkg-plist
+18-405 files

FreeBSD/ports 9f9d29ddevel/sdl20 Makefile, devel/sdl3 Makefile

devel/sdl{20,3}: fix fcitx dependency

- Switch from lib to run-dependency, as only dbus service from fcitx is in fact used by sdl
- Update from deprecated chinese/fcitx to textproc/fcitx5

PR:             293861
Reported by:    jcfyecrayz at liamekaens.com
DeltaFile
+2-1devel/sdl20/Makefile
+2-1devel/sdl3/Makefile
+4-22 files

LLVM/project 27c04fdclang-tools-extra/clang-doc BitcodeReader.cpp BitcodeReader.h

[clang-doc] Simplify parsing and reading bitcode blocks

Much of the logic int he readBlock implementation is boilerplate, and is
repeated for each implementation/specialization. This will become much
worse as we introduce new custom block reading logic as we migrate
towards arena allocation. In preparation for that, we're introducing the
change in logic now, which should make later refactoring much more
straightforward.
DeltaFile
+103-120clang-tools-extra/clang-doc/BitcodeReader.cpp
+5-0clang-tools-extra/clang-doc/BitcodeReader.h
+1-1clang-tools-extra/clang-doc/Representation.h
+109-1213 files

LLVM/project a66cd92clang-tools-extra/clang-doc Generators.h ClangDoc.cpp, clang-tools-extra/clang-doc/benchmarks ClangDocBenchmark.cpp

[clang-doc] Move non-arena allocated types off the OwnedPtr alias

Some types should not be using this alias, which was over applied to
APIs that wont participate in arena style allocation. This patch
restores them to their correct spelling.
DeltaFile
+7-7clang-tools-extra/clang-doc/Generators.h
+4-4clang-tools-extra/clang-doc/ClangDoc.cpp
+4-4clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
+3-3clang-tools-extra/clang-doc/HTMLGenerator.cpp
+2-2clang-tools-extra/clang-doc/benchmarks/ClangDocBenchmark.cpp
+1-1clang-tools-extra/clang-doc/Generators.cpp
+21-211 files not shown
+22-227 files

LLVM/project dae1e80clang-tools-extra/clang-doc Representation.cpp Representation.h, clang-tools-extra/clang-doc/tool ClangDocMain.cpp

[clang-doc] Merge data into persistent memory

We have a need for persistent memory for the final info. Since each
group processes a single USR at a time, every USR is only ever processed by
a single thread from the thread pool. This means that we can keep per
thread persistent storage for all the info. There is significant
duplicated data between all the serialized records, so we can just merge
the final/unique items into the persistent arena, and clear out the
scratch/transient arena as we process each record in the bitcode.

The patch adds some APIs to help with managing the data, merging, and
allocation of data in the correct arena. It also safely merges and deep
copies data from the transient arenas into persistent storage that is
never reset until the program completes.

This patch reduces memory by another % over the previous patches,
bringing the total savings over the baseline to 57%. Runtime performance
and benchmarks stay mostly flat with modest improvements.


    [31 lines not shown]
DeltaFile
+134-10clang-tools-extra/clang-doc/Representation.cpp
+25-25clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
+7-0clang-tools-extra/clang-doc/Representation.h
+166-353 files

LLVM/project ad3d2b2clang-tools-extra/clang-doc Representation.cpp Representation.h

[clang-doc] Support deep copy between arenas for merging

Upcoming changes to the merge step will necessitate that we clear the
transient arenas and merge new items into the persistent arena. However
there are some challenges with that, as the existing types typically
don't want to be copied. We introduce some new APIs to simplify that
task and ensure we don't accidentally leak memory.

On the performance front, we reclaim about 2% of the overhead, bringing
the cumulative overhead from the series of patches down to about 7% over
the baseline.

| Metric | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |
| Time | 920.5s | 1014.5s | 991.5s | +7.7% | -2.3% |
| Memory | 86.0G | 39.9G | 40.0G | -53.4% | +0.3% |

| Benchmark | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |

    [28 lines not shown]
DeltaFile
+140-21clang-tools-extra/clang-doc/Representation.cpp
+30-0clang-tools-extra/clang-doc/Representation.h
+170-212 files

LLVM/project 91e9881clang-tools-extra/clang-doc BitcodeReader.cpp Serialize.cpp, clang-tools-extra/unittests/clang-doc SerializeTest.cpp MergeTest.cpp

[clang-doc] Move Info types into arenas

Info types used to own significant chunks of data. As we move these into
local arenas, these types must be trivially destructible, to avoid
leaking resources when the arena is reset. Unfortunaly, there isn't a
good way to transition all the data types one at a time, since most of
them are tied together in some way. Further, as they're now allocated in
the arenas, they often cannot be treated the same way, and even the
aliases and interfaces put in pLace to simplify the transition cannot
cover the full range of changes required.

We also use some SFINAE tricks to avoid adding boilerplate for helper
APIs, we'd otherwise ahve to support

Though it introduces some additional churn, we also try to keep tests
from using arena allocation as much as possible, since this is not
required to test the implementation of the library. As much of the test
code needed to be rewritten anyway, we take the opportunity to
transition now.

    [41 lines not shown]
DeltaFile
+419-187clang-tools-extra/clang-doc/BitcodeReader.cpp
+246-189clang-tools-extra/unittests/clang-doc/SerializeTest.cpp
+196-129clang-tools-extra/unittests/clang-doc/MergeTest.cpp
+176-80clang-tools-extra/unittests/clang-doc/ClangDocTest.cpp
+137-75clang-tools-extra/clang-doc/Serialize.cpp
+71-41clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
+1,245-70114 files not shown
+1,662-95220 files

LLVM/project 2800ab6clang-tools-extra/clang-doc Representation.cpp

[clang-doc] Consolidate merging logic

As we migrate things in the arena, this logic may get more complex.
Factoring it out now, will give clear extension points to make this
easier to manage.
DeltaFile
+10-9clang-tools-extra/clang-doc/Representation.cpp
+10-91 files

LLVM/project b735105clang-tools-extra/clang-doc Representation.h

[clang-doc] Enforce arena allocated types are trivially destructible

We can enforce at compile-time that the types we want to place in the
arenas are always safe to allocate there.
DeltaFile
+26-0clang-tools-extra/clang-doc/Representation.h
+26-01 files

LLVM/project 671b28dclang-tools-extra/clang-doc BitcodeReader.cpp Serialize.cpp, clang-tools-extra/unittests/clang-doc MDGeneratorTest.cpp BitcodeTest.cpp

[clang-doc] Make CommentInfo arena allocated

This patch move the CommentInfo type into the arena. It updates block
handling to collect child info types and serialize the array in one
shot.

We also clean up the test code to avoid using the arenas in the tests.
This has the upside of making the test more hermetic, and avoids churn
in the related code as the allocation API interfaces evolve.

Performance and memory usage regress slightly. This is somewhat expected
as we do not yet aggressively release short term memory during merge
operations. Future patches will reclaim this overhead.

| Metric | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |
| Time | 920.5s | 998.5s | 1010.5s | +9.8% | +1.2% |
| Memory | 86.0G | 43.8G | 47.8G | -44.4% | +9.2% |


    [26 lines not shown]
DeltaFile
+124-94clang-tools-extra/unittests/clang-doc/MDGeneratorTest.cpp
+70-111clang-tools-extra/unittests/clang-doc/BitcodeTest.cpp
+66-103clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
+15-30clang-tools-extra/unittests/clang-doc/MergeTest.cpp
+17-9clang-tools-extra/clang-doc/BitcodeReader.cpp
+15-5clang-tools-extra/clang-doc/Serialize.cpp
+307-3526 files not shown
+345-37012 files

LLVM/project d5bead9clang-tools-extra/clang-doc Representation.cpp Representation.h, clang-tools-extra/unittests/clang-doc MergeTest.cpp ClangDocTest.cpp

[clang-doc] Migrate Namespaces to arena allocation

This patch allocates the NamespaceInfo types in the local arenas, and
adapts the merging logic for the new list type and its children.
Memory use and performance improve slightly. Micro-benchmarks show a
regression in merge operations due to the more complex list operations.

 ## Build Clang-Doc Documentation
| Metric | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |
| Time | 920.5s | 1009.2s | 1002.4s | +8.9% | -0.7% |
| Memory | 86.0G | 43.2G | 43.9G | -49.0% | +1.6% |

 ## Microbenchmarks (Filtered for >1% Delta)
| Benchmark | Baseline | Prev | This | Culm% | Seq% |
| :--- | :--- | :--- | :--- | :--- | :--- |
| BM_BitcodeReader_Scale/10 | 67.9us | 69.7us | 69.3us | +1.9% | -0.7% |
| BM_BitcodeReader_Scale/10000 | 70.5ms | 22.3ms | 24.8ms | -64.8% | +11.4% |
| BM_BitcodeReader_Scale/4096 | 23.2ms | 4.7ms | 4.4ms | -80.9% | -5.7% |

    [22 lines not shown]
DeltaFile
+26-1clang-tools-extra/clang-doc/Representation.cpp
+8-8clang-tools-extra/unittests/clang-doc/MergeTest.cpp
+8-2clang-tools-extra/clang-doc/Representation.h
+7-3clang-tools-extra/unittests/clang-doc/ClangDocTest.cpp
+6-3clang-tools-extra/clang-doc/JSONGenerator.cpp
+4-4clang-tools-extra/unittests/clang-doc/SerializeTest.cpp
+59-217 files not shown
+83-3713 files

LLVM/project 4ad1844clang-tools-extra/clang-doc BitcodeReader.cpp BitcodeWriter.cpp

[clang-doc] Refactor FriendInfo parameters to use ArrayRef (#190047)

This also adapts readBlock for the new layouts.
DeltaFile
+45-7clang-tools-extra/clang-doc/BitcodeReader.cpp
+2-3clang-tools-extra/clang-doc/BitcodeWriter.cpp
+2-2clang-tools-extra/clang-doc/JSONGenerator.cpp
+1-2clang-tools-extra/clang-doc/Serialize.cpp
+1-1clang-tools-extra/clang-doc/Representation.h
+51-155 files

FreeNAS/freenas 916709csrc/middlewared/middlewared/plugins/filesystem_ acl_template.py

NAS-140530 / 26.0.0-BETA.2 / Auto-expand builtin ACL templates with groups (by anodos325) (#18642)

This commit changes the default behavior of our ACL templates to
auto-expand to include users / admins. It restores behavior from earlier
truenas versions (where UI was auto-expanding stored ACL templates with
these accounts). The UI behavior was reverted back due to problems
raised by automation team. In this case I'm reintroducing due to desire
to make ACL templates easier for our user base (since most of them just
want their local / AD users to be able to access data).

Original PR: https://github.com/truenas/middleware/pull/18630

---------

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+14-5src/middlewared/middlewared/plugins/filesystem_/acl_template.py
+14-51 files

LLVM/project b8ea714lldb/source/Core ModuleList.cpp

[lldb] Fix formatting in ModuleList (NFC) (#190382)

I had auto-merge enabled in #189444 and since the formatter is
non-blocking it got merged despite the issue. Given I'm already here, I
just formatted the whole file.
DeltaFile
+6-9lldb/source/Core/ModuleList.cpp
+6-91 files

FreeNAS/freenas df6cd50src/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

NAS-140540 / 26.0.0-BETA.2 / fix R60 enclosure mapping (by yocalebo) (#18645)

We have another internal R60 that doesn't show any enclosures at all.
The reason why is that its system product name (in DMI table) is flashed
with the `-SC` suffix....

This was supposed to have been accounted for in
https://github.com/truenas/middleware/commit/5adab5d81bd8e2996828b7b32193c7a87548ff1d
and we even tested on another internal R60 platform and IT WORKED.

The issue is that the R60 that was tested against is NOT flashed with
any suffixes.... which revealed the fact that the nvme mapping code did
not follow same logic and the R60 is an all NVMe system. To remedy the
situation add a utility function that unifies the model transformation
into 1 place so, ideally, this won't be as easy to do in the future....

Original PR: https://github.com/truenas/middleware/pull/18641

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

FreeNAS/freenas 4c9198esrc/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

NAS-140540 / 26.0.0-BETA.1 / fix R60 enclosure mapping (by yocalebo) (#18644)

We have another internal R60 that doesn't show any enclosures at all.
The reason why is that its system product name (in DMI table) is flashed
with the `-SC` suffix....

This was supposed to have been accounted for in
https://github.com/truenas/middleware/commit/5adab5d81bd8e2996828b7b32193c7a87548ff1d
and we even tested on another internal R60 platform and IT WORKED.

The issue is that the R60 that was tested against is NOT flashed with
any suffixes.... which revealed the fact that the nvme mapping code did
not follow same logic and the R60 is an all NVMe system. To remedy the
situation add a utility function that unifies the model transformation
into 1 place so, ideally, this won't be as easy to do in the future....

Original PR: https://github.com/truenas/middleware/pull/18641

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

FreeNAS/freenas 355af4bsrc/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

NAS-140540 / 25.10.2.2 / fix R60 enclosure mapping (by yocalebo) (#18643)

We have another internal R60 that doesn't show any enclosures at all.
The reason why is that its system product name (in DMI table) is flashed
with the `-SC` suffix....

This was supposed to have been accounted for in
https://github.com/truenas/middleware/commit/5adab5d81bd8e2996828b7b32193c7a87548ff1d
and we even tested on another internal R60 platform and IT WORKED.

The issue is that the R60 that was tested against is NOT flashed with
any suffixes.... which revealed the fact that the nvme mapping code did
not follow same logic and the R60 is an all NVMe system. To remedy the
situation add a utility function that unifies the model transformation
into 1 place so, ideally, this won't be as easy to do in the future....

Original PR: https://github.com/truenas/middleware/pull/18641

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

FreeNAS/freenas a63f2e5src/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

fix R60 enclosure mapping

(cherry picked from commit d7ccdee3899f1e4791c2ff166bd947268eaa05bc)
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

FreeNAS/freenas 7485878src/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

fix R60 enclosure mapping

(cherry picked from commit d7ccdee3899f1e4791c2ff166bd947268eaa05bc)
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

FreeNAS/freenas 820c8dcsrc/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

fix R60 enclosure mapping

(cherry picked from commit d7ccdee3899f1e4791c2ff166bd947268eaa05bc)
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

FreeNAS/freenas fe55c60src/middlewared/middlewared/plugins/enclosure_ constants.py utils.py

NAS-140540 / 27.0.0-BETA.1 / fix R60 enclosure mapping (#18641)

We have another internal R60 that doesn't show any enclosures at all.
The reason why is that its system product name (in DMI table) is flashed
with the `-SC` suffix....

This was supposed to have been accounted for in
https://github.com/truenas/middleware/commit/5adab5d81bd8e2996828b7b32193c7a87548ff1d
and we even tested on another internal R60 platform and IT WORKED.

The issue is that the R60 that was tested against is NOT flashed with
any suffixes.... which revealed the fact that the nvme mapping code did
not follow same logic and the R60 is an all NVMe system. To remedy the
situation add a utility function that unifies the model transformation
into 1 place so, ideally, this won't be as easy to do in the future....
DeltaFile
+19-11src/middlewared/middlewared/plugins/enclosure_/constants.py
+10-0src/middlewared/middlewared/plugins/enclosure_/utils.py
+3-5src/middlewared/middlewared/plugins/enclosure_/enclosure_class.py
+2-2src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+34-184 files

OpenZFS/src a715722. AUTHORS

AUTHORS: add Christos Longros

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Christos Longros <chris.longros at gmail.com>
Closes #18396
DeltaFile
+1-0AUTHORS
+1-01 files

LLVM/project f29d238offload/ci openmp-offload-amdgpu-clang-flang.py

[Buildbot][AMDGPU] Adapt to recent CMake change (#190381)

Make changes to adapt to
https://github.com/llvm/llvm-project/pull/190349
DeltaFile
+1-1offload/ci/openmp-offload-amdgpu-clang-flang.py
+1-11 files

LLVM/project 6111520clang-tools-extra/clang-tidy/readability IdentifierNamingCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix readability-identifier-naming for C++17 structured bindings (#189500)

`BindingDecl` nodes, i.e. the individual names in a structured binding,
were not handled in `IdentifierNamingCheck::findStyleKind()`, causing
them to fall through to the Default style or be silently ignored.
This led to incorrect renames, e.g. applying member variable conventions
to local bindings.

---------

Signed-off-by: Björn Svensson <bjorn.a.svensson at est.tech>
DeltaFile
+26-0clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp
+9-0clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+39-03 files

FreeNAS/freenas 2734d08src/middlewared/middlewared/plugins/filesystem_ acl_template.py

Auto-expand builtin ACL templates with groups

This commit changes the default behavior of our ACL templates to
auto-expand to include users / admins. It restores behavior from
earlier truenas versions (where UI was auto-expanding stored
ACL templates with these accounts). The UI behavior was reverted
back due to problems raised by automation team. In this case I'm
reintroducing due to desire to make ACL templates easier for
our user base (since most of them just want their local / AD
users to be able to access data).

(cherry picked from commit 08ec693d7f40a47052801a6d78bb7a53e324b8fd)
DeltaFile
+12-1src/middlewared/middlewared/plugins/filesystem_/acl_template.py
+12-11 files