[ValueTracking] Treat RISC-V vsetvlimax as a power of two (#218831)
VLMAX = VLEN * LMUL / SEW is always a non-zero power of two for any valid
vtype, so llvm.riscv.vsetvlimax is a power of two regardless of SEW/LMUL or
whether a vscale_range is present. Report this in isKnownToBeAPowerOfTwo
so that consumers such as ctpop and the x & (x - 1) idiom can fold.
Assisted-by: TRAE CLI (Opus 4.8)
[ExpandMemCmp] Apply NumLoadsPerBlock to ordering compares (#215186)
Make NumLoadsPerBlock control both equality and ordering memcmp
expansions. For ordering comparisons, pack consecutive legal loads
in memory order into a value no wider than the target preferred
load width, then compare the packed values. This preserves
lexicographic semantics while reducing conditional branches.
BPF uses groups of eight byte-load pairs, so an align-1 32-byte
comparison forms four i64 compare blocks instead of 32 byte compare
blocks.
Other targets retain their existing default ordering behavior unless
grouping is explicitly requested.
Assisted-by: TRAE CLI (GPT-5)
security/vuxml: add FreeBSD SAs issued on 2026-08-25
FreeBSD-SA-26:56.hwpmc affects all supported releases
FreeBSD-SA-26:57.unix affects 15.0R and 15.1R
FreeBSD-SA-26:58.sound affects all supported releases
FreeBSD-SA-26:59.mac_do affects 15.0R and 15.1R
FreeBSD-SA-26:60.ppp affects all supported releases
FreeBSD-SA-26:62.tty affects all supported releases
FreeBSD-SA-26:63.posixshm affects all supported releases
[Github] Bump formatting/tools container to 23.1.0 (#218815)
Now that 23.1.0 has been released, we should update the container to
ensure we're using the latest released version of the tooling.
[Github] Hash pin ci-format container (#218816)
This follows our own CI best practices and ensures zizmor/CodeQL will
not complain about this when people inevitably touch it in the future.
[RISCV][Verifier] Check operands and result type of RISC-V vsetvli/vsetvlimax (#218594)
The result of `llvm.riscv.vsetvli/vsetvlimax` models VLMAX (or a VL bounded
by it) and is only defined for XLen, so the result type must be i32 or i64.
Narrower types cannot represent the architectural VLMAX range of [1, 65536]
that value analyses rely on.
Also check that the VSEW and VLMUL immediate operands encode a valid
SEW/LMUL pair (VSEW <= 3, VLMUL != reserved), so that consumers can
assume a well-formed vtype.
Assisted-by: TRAE CLI (Opus 4.8)
[C++][Modules] Don't insert `#include` before GMF when `-include` used (#212533)
Clang currently emits command-line implicit inputs such as `-imacros`,
`-include-pch`/`-include-pth`, and `-include` as part of the predefines
buffer. This causes them to be processed before the main source file.
For a C++20 module unit with a global module fragment:
```cpp
module;
export module M;
```
a force-included header containing declarations was effectively
processed as:
```cpp
#include "Header.h"
module;
[23 lines not shown]
[X86] Limit the result of XOR8rr_NOREX unused (#218640)
In case it may be zero/sign-extended into an REX/REX2 register.
Fixes: #218583
Assisted-by: Claude Opus 4.8
[MCParser,test] Improve macro argument charset test (#218828)
'@', '#', and '?' are assembly identifier characters, but they terminate
a macro argument name.
nfs: New sysctl node vfs.nfsd.maxexportspermount.
Limits the number of different ways a single mount point can be
exported. Default is limited to 256; can be expanded by sysctl up to
anything that won't overflow kva.
XXX Should prevent increasing it at securelevel>0.
PR kern/60645: nfssvc(2): arithmetic overflow in input array sizing
[AMDGPU] Correct DS FIFO buffer size semantics
There was some ambiguity in how buffersize 0 and 1 are handled. The
correct semantics are:
- `BufferSize == 0`: unlimited, no FIFO stall
- `BufferSize == 1`: unbuffered, only one instruction in flight
- `BufferSize > 1`: buffered FIFO
Handle DS FIFO accounting edge cases
Saturate hardware-unit pressure decrements and treat buffer sizes zero
and one as disabling buffering to avoid underflow and inconsistent stall
costs.
[AMDGPU] Use DS latency for FIFO scheduling
Use instruction latency for DS hardware-unit cycle accounting so the FIFO
model can identify a full buffer. Add focused MIR coverage for the resulting
stall cost and scheduling decision, and regenerate the integration checks.
Change-Id: I2f4df2e97d145af4935872dbd43108e1b55077ab
