[VPlan] Remove the unused CalculateTripCountMinusVF opcode (NFC) (#216675)
bcc272b3220f ("[LV] Remove DataAndControlFlowWithoutRuntimeCheck. NFC",
#183762) removed the only createNaryOp building this opcode, leaving
behind the enum entry and its cases for type inference, operand count,
scalar generation, lowering and printing. Nothing constructs it, so no
plan can contain it and no test prints it.
PowerPC: Fix MI peephole crash on an undef forwarding operand
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Support [[clang::lifetime_capture_by(X)]] in Plain Containers (#204361)
This PR implements support for `[[clang::lifetime_capture_by(X)]]` to
enable tracking lifetimes for plain structs and containers like
`std::vector` without requiring manual `[[gsl::Pointer]]` or
`[[gsl::Owner]]` annotations. The implementation extends the
`LifetimeAnnotatedOriginTypeCollector` to register types in capture_by
contracts for origin tracking.
This PR also enables the intra-procedural analysis in existing tests
using -Wlifetime-safety and updated expectations to handle the more
detailed flow-sensitive diagnostics.
```cpp
struct MyContainer {
const char* stored_ptr;
};
void captureInto(std::string_view v [[clang::lifetime_capture_by(c)]], MyContainer& c);
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GlobalISel: Use MIPatternMatch in GIMatchTableExecutor (#216601)
Replace the getVRegDef + opcode-check idiom in isBaseWithConstantOffset
with mi_match using m_GPtrAdd and m_GConstant.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
RuntimeLibcalls: Provide fp128 long double libcalls on X86 (#216622)
16a8d8d038a3 removed the l-suffixed long double math functions
from the default set and re-added them per-target gated on
isLongDoubleF128, but X86 was not given the re-add. On targets
whose long double is fp128 (e.g. x86_64 Android/OHOS) this dropped
the fp128 l-suffixed libcalls.
Fixes the regression reported on #214944.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[AMDGPU] Fix isKnownNeverNaN for FMIN_LEGACY/FMAX_LEGACY (#216338)
These compare-selects return one of the operands bit-for-bit, so a
signaling NaN operand passes through unquieted
Recurse into both operands instead of assuming never-sNaN
[AArch64][BOLT] Fold local-exec TLS relocations into loads and stores (#215531)
Emit the low part of the 12- and 24-bit local-exec sequences as an
ADDlow so that it folds into the addressing mode of a following load or
store, saving one instruction.
This re-lands the local-exec part of r327316 (7bc64bd889ad), whose ELF
changes r327503 (bde677289acc) reverted because neither LLD nor GNU
binutils implemented the relevant
R_AARCH64_TLSLE_LDST*_TPREL_LO12 relocations at the time.
LLD and GNU bfd now handle the non-checking 8- to 64-bit variants used
by the default 24-bit sequence. GNU bfd also handles the checked
variants used by the 12-bit sequence; LLD does not support those, but it
did not support the predecessor checked ADD relocation either. GNU bfd
still has no LDST128 support, so 128-bit accesses stay unfolded.
Teach BOLT to classify the folded TLS load/store relocations so it can
process binaries linked with --emit-relocs.
[ARM] Emit an error when the hard-float ABI is enabled but can't be used (#111334)
Prior to this, compiling for an eabihf target with a CPU lacking
floating-point registers would silently use the soft-float ABI instead,
even though the Arm attributes section would still have
"Tag_ABI_VFP_args: VFP registers", which leads to silent ABI mismatches
at link time.
Update various tests that were using inconsistent ABI/PCS and features.
Change ARMTargetLowering::getEffectiveCallingConv from private to public
and modify it to pass through unrecognized calling conventions. Now that
ARMBaseTargetMachine::createMachineFunctionInfo calls it, leaving a
fatal error would change the behavior of IR passes that do not need to
lower calling conventions. Unrecognized calling conventions are still
treated as errors in lowering.
Fixes #110383.
[libc] Fix {asc,c,gm,mk}time(_r)? tests and spurios snprintf call (#216423)
time_test_utils was depending on a non-existent library, which caused
these tests to be auto-skipped. Fixing that exposed the fact that some
of the tests don't build (in hermetic mode) due to a snprintf
dependency concealed behind a __builtin_snprintf in asctime.
This patch addresses the existing TODO by moving
asctime to asctime_utils.h (avoiding a dependency loop)
and implementing it via strftime_main.
Assisted by Gemini.
clang/AMDGPU: Don't emit target-features on AMDGCN-flavored SPIR-V
The spirv64-amd-amdhsa target unions every GPU's features in its feature
map so it can report builtins as available. The CodeGen doesn't have
any use of the target-features. Putting it into the IR just results
in an annoying to update test every time a new feature is added. The
ultimate SPIRV codegen doesn't do anything with it, and if it did
survive to AMDGPU codegen, it would be actively harmful.
This isn't an ideal solution. The target-features spam is also
noisy and useless in the AMDGPU case, but solving that is more
intricate because we do currently rely on this for some features,
most notably the wavesize.
Co-authored-by: Claude (Claude-Opus-4.8)
py-wcmatch: updated to 11.0.1
11.0.1
- **DOCS**: Provide information in documentation that discloses information about what should or should not be
expected from Wildcard Match in regards to security, and provide general information to allow users to make good
decisions.
- **FIX**: Fix an issue where in some cases dot handling was not correct within an extended glob pattern when
`EXTGLOB`/`EXTMATCH` was enabled.
clang/AMDGPU: Use feature bitset instead of ArchAttr
Convert from the legacy getArchAttrAMDGCN manual bitmask checks to using
the new generated bitset. These are the easy cases. sramecc and xnack
require more supporting work so will be done later.
Co-authored-by: Claude (Claude-Opus-4.8)
[clang][CIR][AArch64] Add lowering for conversion intrinsics (#211609)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
It continues the work started in #190961, #193273, #199990 and #209252.
This PR implements the remaining conversions truncating to zero:
* vcvts_s32_f32
* vcvts_s64_f32
* vcvts_u32_f32
* vcvts_u64_f32
The corresponding tests are moved from:
* clang/test/CodeGen/AArch64/
to:
* clang/test/CodeGen/AArch64/neon/
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp
GlobalISel: Match loads by pointer operand in CombinerHelper
Add a load matcher that binds the pointer operand (like IR's m_Load), with
optional outputs for the load instruction and its MachineMemOperand via m_MMO.
Use it to replace the getVRegDef + dyn_cast idiom in the load combines.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
GlobalISel: Migrate misc. CombinerHelper def checks to MIPatternMatch
Replace getVRegDef + cast/opcode-check idioms across CombinerHelper
with mi_match, adding named instruction binders and operand-form matchers
as needed.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[mlir][affine] Require a vector size in affine-super-vectorize (#171110)
Diagnose invocations that omit the `virtual-vector-size` option. A
vector rank is required to construct a vectorization pattern, so
accepting an empty size list would silently leave the input unchanged.
Check that vector sizes are present and positive before applying
rank-dependent constraints.
Fixes #114528
GlobalISel: Use MIPatternMatch in GIMatchTableExecutor
Replace the getVRegDef + opcode-check idiom in isBaseWithConstantOffset with
mi_match using m_GPtrAdd and m_GConstant.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
