LLVM/project 83826c5llvm/test/CodeGen/Generic llvm-ct-intrinsics.ll 2008-02-04-Ctlz.ll

SPARC: Disable generic codegen tests that depend on libcalls

The module doesn't get the triple set without any target argument,
so the assumed set of libcalls is empty
DeltaFile
+1-0llvm/test/CodeGen/Generic/llvm-ct-intrinsics.ll
+1-0llvm/test/CodeGen/Generic/2008-02-04-Ctlz.ll
+2-02 files

LLVM/project 5ca6ab9llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVTargetTransformInfo.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-zvdot4a8i-i64.ll zvdot4a8i-i64-sdnode.ll

Match lowering and add more tests

Created using spr 1.3.6-beta.1
DeltaFile
+24-464llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-i64-sdnode.ll
+452-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i-i64.ll
+97-5llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-costs.ll
+47-4llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+25-7llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+645-4805 files

LLVM/project bd9c0ebllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-zvdot4a8i-i64.ll zvdot4a8i-i64-sdnode.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+24-464llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-i64-sdnode.ll
+452-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i-i64.ll
+25-7llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+501-4713 files

LLVM/project 1f6b652libc/shared/math roundf128.h, libc/src/__support/math roundf128.h

[libc] Modify `roundf128` to use emulated Float128 type (#216563)
DeltaFile
+18-0libc/test/src/math/roundf128_test.cpp
+15-0libc/test/src/math/CMakeLists.txt
+4-7libc/src/__support/math/roundf128.h
+0-6libc/shared/math/roundf128.h
+5-1libc/test/src/math/smoke/roundf128_test.cpp
+6-0utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
+48-1422 files not shown
+82-2828 files

LLVM/project d4c1935libclc/clc/lib/spirv CMakeLists.txt

[libclc] Use generic subnormal_config for spirv-vulkan (#217240)

Since clspv properly handles denorm with
https://github.com/google/clspv/pull/1616
we should rely on the generic implementation of subnormal_config.
DeltaFile
+4-1libclc/clc/lib/spirv/CMakeLists.txt
+4-11 files

NetBSD/pkgsrc-wip 570df05webkit-gtk60 Makefile PLIST

webkit-gtk60: update to 2.52.6.

  - Improve memory usage in pages that use font variations.
  - The webkit://gpu page now respects the dark theme user preference.
  - Fix cross compilation due to failure to pick the correct gio-unix-2.0
    headers in certain configurations.
  - Fix calculating data sizes of reported through WebKitWebsiteData.
  - Fix the build with CMake 4.4 or newer.
  - Fix several crashes and rendering issues.
DeltaFile
+3-3webkit-gtk60/distinfo
+2-2webkit-gtk60/PLIST
+1-1webkit-gtk60/Makefile
+6-63 files

FreeBSD/ports b496a8cwww/opengist Makefile distinfo

www/opengist: Update to 1.15.1

Changes since 1.14.0:

v1.15.1

Fixed

  * Admin pagination with new URLs (#782).
  * Stop unbounded diff content growth for large files (#787).

v1.15.0

Added

  * UI rework (#757).
  * Gist settings page, with metadata edition and danger zone (#757).
  * Explore users page, with search and sorting (#757).
  * Explore topics page (#757).

    [19 lines not shown]
DeltaFile
+7-7www/opengist/distinfo
+1-1www/opengist/Makefile
+8-82 files

OpenBSD/ports exWjDLGdevel/fmt Makefile, devel/fmt/patches patch-include_fmt_format_h

   fmt: fix build with libcxx22, ok sthen

   fmt relies on pulling in stdlib.h for malloc/free via C++ headers, and this
   no longer happens with libcxx22. So follow the approach taken by upstream
   and include it explicitly.
VersionDeltaFile
1.1+21-0devel/fmt/patches/patch-include_fmt_format_h
1.8+1-0devel/fmt/Makefile
+22-02 files

LLVM/project 6c206e3llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU sched-dynamic-vgpr-blocks.mir

[AMDGPU] Fix refactoring mishap (#216974)

We ended up calling getAllocatedNumVGPRBlocks with the arguments in the
wrong order - it should take the number of VGPRs first, and then the
size of a dynamic VGPR block.

Assisted-by: Claude
DeltaFile
+72-0llvm/test/CodeGen/AMDGPU/sched-dynamic-vgpr-blocks.mir
+3-3llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+75-32 files

LLVM/project fd0d6dallvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, mlir/test/Target/LLVMIR omptarget-debug-declare-mapper.mlir

[OMPIRBuilder] Don't use invalid debug loc in declare mapper function. (#148263)

This is similar to https://github.com/llvm/llvm-project/pull/147950 but
for declare mapper function.
DeltaFile
+50-0mlir/test/Target/LLVMIR/omptarget-debug-declare-mapper.mlir
+2-2llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+52-22 files

LLVM/project 437a849llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+24-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2-3llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+37-143 files

LLVM/project 72cc539llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project e78974fllvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project e2fa7d5llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+1-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-01 files

LLVM/project 012970dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize blend-i1.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+29-253 files

LLVM/project 71b39c0llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/VPlan constant-fold.ll

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+116-153llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-11llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+116-1642 files

LLVM/project 3b39559llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Update trunc combine, fix m_Not return position
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-41 files

LLVM/project de2b9f8clang/docs ReleaseNotes.md, clang/lib/Sema SemaRISCV.cpp

[Clang][RISCV] Allow three SiFive CLIC interrupt arguments (#216159)

The SiFive CLIC interrupt values may be combined with each other and
with the machine value, but the interrupt attribute previously accepted
at most two arguments.

This commit allows three arguments for the combination of machine,
SiFive-CLIC-preemptible, and SiFive-CLIC-stack-swap.

Fixes #216138
DeltaFile
+14-1clang/test/Sema/riscv-interrupt-attr-sifive.c
+12-0clang/test/Sema/riscv-interrupt-attr-qci.c
+4-4clang/lib/Sema/SemaRISCV.cpp
+5-1clang/test/Sema/riscv-interrupt-attr.c
+6-0clang/test/Sema/riscv-interrupt-attr-rnmi.c
+3-0clang/docs/ReleaseNotes.md
+44-66 files

LLVM/project 7271360llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 psadbw.ll shrink_vmul.ll

[X86] isTargetShuffleEquivalent - only use "known zero" element if its known never poison/undef as well (#217030)

We're starting to hit cases where we've used AND/ANDNP masking to zero
out vector elements, but SimplifyDemandedElts assumes the element is
unused, folds to poison and then later folds AND(poison,0) -> poison.

This needs a more thorough cleanup of a number of x86 folds that do this
(similar to #215538), but that would result in a great deal of churn,
and it looks like a #214388 fix requires backporting to 23.x.

So initially I'm taking the approach that @xyyy1420 found so we can get
this backported and I can then address the issue more thoroughly in
trunk. I'm not convinced that this will address all poison cases, but
I'm reluctant to attempt a larger backport patch.

Fixes #214388
DeltaFile
+1,014-1,012llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+122-0llvm/test/CodeGen/X86/pr214388.ll
+41-39llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
+4-12llvm/test/CodeGen/X86/psadbw.ll
+13-3llvm/test/CodeGen/X86/shrink_vmul.ll
+6-2llvm/lib/Target/X86/X86ISelLowering.cpp
+1,200-1,0682 files not shown
+1,205-1,0688 files

LLVM/project 3c6befelibc/src/__support/math atan2f128.h, libc/src/math/generic atan2l.cpp

[libc] Modify `atan2f128` to use emulated Float128 type  (#216508)
DeltaFile
+37-13libc/test/src/math/smoke/atan2f128_test.cpp
+10-13libc/src/__support/math/atan2f128.h
+10-7libc/test/src/math/atan2f128_test.cpp
+14-0utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
+2-7libc/src/math/generic/atan2l.cpp
+8-0utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
+81-4022 files not shown
+116-6028 files

NetBSD/pkgsrc Wn2DvY6textproc/tabiew Makefile cargo-depends.mk

   tabiew: update to 0.14.2.

   About a month of development.
VersionDeltaFile
1.9+454-481textproc/tabiew/distinfo
1.9+150-159textproc/tabiew/cargo-depends.mk
1.9+2-2textproc/tabiew/Makefile
+606-6423 files

LLVM/project 83d061allvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+24-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2-3llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+37-143 files

LLVM/project a9a62a6llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 9cf47b1llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize blend-i1.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+29-253 files

LLVM/project 84ace96llvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project 21db570llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/VPlan constant-fold.ll

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+116-153llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-11llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+116-1642 files

LLVM/project 4ad24a0llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Update trunc combine, fix m_Not return position
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-41 files

OpenBSD/ports hBFOtbDnet/py-idna Makefile distinfo

   update to py3-idna-3.19
VersionDeltaFile
1.20+2-2net/py-idna/distinfo
1.34+1-1net/py-idna/Makefile
+3-32 files

OpenBSD/ports gjxtLBtsysutils/py-dotenv Makefile distinfo

   update to py3-dotenv-1.2.3
VersionDeltaFile
1.11+2-2sysutils/py-dotenv/distinfo
1.19+1-1sysutils/py-dotenv/Makefile
+3-32 files

FreeBSD/ports dc20e3cwww/opengist distinfo Makefile, www/opengist/files patch-package.json opengist.in

www/opengist: Update to v1.14.0

- Remove assets dir, they are already bundled in the binary
- Fix the broken rc service that would not shut down correctly
- Move the pidfiles to /var/run/ to avoid needing to create a dir
- Use the prebuilt frontend assets published upstream, dropping the
  npm build dependency
- Enable aarch64

Reviewed by:    fox
Differential Revision:  https://reviews.freebsd.org/D58255
DeltaFile
+0-79www/opengist/pkg-plist
+15-40www/opengist/Makefile
+28-14www/opengist/files/opengist.in
+7-7www/opengist/distinfo
+0-13www/opengist/files/patch-package.json
+50-1535 files